The ADF4378 high performance PLL has a −239 dBc/Hz: normalized in-band phase noise floor, ultra-low 1/f noise, and a high phase/frequency detector (PFD) frequency that can achieve ultralow in-band noise and integrated jitter. The fundamental VCO and output divider of the ADF4378 generate frequencies from 800 MHz to 12.8 GHz. The ADF4378 integrates all necessary power-supply bypass capacitors, which saves board space on compact boards.
For multiple data converter and MxFE clock applications, the ADF4378 simplifies clock alignment and calibration routines required with other clock solutions by implementing the automatic reference to output synchronization feature, the matched reference to output delays across process, voltage, and temperature feature, and the less than ±0.1 ps, jitter free reference to output delay adjustment capability feature.
The general-purpose pulse retimer feature allows for predictable and precise multichip clock and pulse alignment for SYSREF, SYNC, and multichip synchronization (MCS) architectures. JESD204B and JESD204C Subclass 1 solutions are supported by pairing the ADF4378 with an integrated circuit (IC) that distributes pairs of reference and SYSREF signals. The pulse retimer feature simplifies the system design by allowing the widely distributed SYSREF to only meet the slower reference frequency timing vs. the much more stringent output clock timing. Serial-peripheral interface (SPI) selectable current-mode logic (CML)/low-voltage positive/pseudo emitter-coupled logic (LVPECL) or low-voltage differential signaling (LVDS) SYSREF input and LVDS SYSREF output allow CML to LVDS signal conversion, which simplifies clock and SYSREF alignment for various converters. The pulse retimer feature also can be used with transceiver MCS signals and SYNC signals for other ICs.
Key Features and Benefits
- Output frequency range: 800 MHz to 12.8 GHz
- Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz)
- Jitter = 27 fsRMS (ADC SNR Method)
- Wideband Noise Floor: -160 dBc/Hz @12 GHz
- PLL Specifications:
- -239 dBc/Hz: Normalized In-Band Phase Noise Floor
- -147 dBc/Hz: Normalized In-Band 1/f Noise
- Phase Detector Frequency up to 500 MHz
- Reference Input Frequency up to 1 GHz
- Typical -100 dBc PFD spurs
- Reference to Output Delay Specifications:
- Part-to-Part Standard Deviation: 3 ps
- Temperature Drift: 0.03 ps/℃
- Adjustment Step Size: < +/-0.1 ps
- Multi-chip Output Phase Alignment
- Retimed LVDS SYSREF output
- 3.3 V and 5 V Power supplies
- 7 mm x 7 mm 48 Lead LGA
Applications
- High Performance Data Converter and MxFE Clocking
- Wireless infrastructure (MC-GSM, 5G)
- Test and Measurement
- FPGA with integrated data converters
Evaluation Board
The ADF4378 can be evaluated with the EVAL-ADF4378.
Block Diagrams and Tables
See related product
See related product