What is Sigma-Delta ADC? Working Principle Explained

The Sigma Delta ADC is a staple, in the tool kit of today’s signal acquisition & processing system designers. The aim of this piece is to give the reader the base knowledge on the fundamental principles behind the Sigma Delta ADC topology. Examples on the trade-offs between noise, bandwidth, settling time all key parameters associated with ADCs subsystem design are explored, to provide context for designers of precision data acquisition circuits.

Sigma Delta Modulator

Typically there are two blocks: the Sigma Delta Modulator and the digital signal processing block, usually a digital filter. This high level block diagram and the key concepts of the Sigma Delta ADC are shown in Figure 1.

Figure 1. Pillar concepts of the Sigma Delta ADC.

As the sigma delta modulator is an oversampled architecture let’s start with the sampling theory and the scenario of Nyquist and oversampled ADC operation.

Figure 2 illustrates the comparison between the Nyquist operation of an ADC with the oversampled case and finally with the Sigma Delta Modulated (also oversampled) case.[1]



Figure 2. Comparing Nyquist, Oversampled and Sigma Delta topologies

“A” represents the quantization noise of an ADC when running in a “straight-Nyquist” operation. In this case the quantization noise is determined by the LSB size of the ADC. “FS” is the sampling rate of the ADC and FS/2 is the Nyquist frequency. Case B shows the same converter, except now it is used in an oversampled context so a faster sampling rate is employed. The sampling rate is increased by a factor of K with the quantization noise now spread over a wider bandwidth up to K×FS/2. The low pass digital filter (typically with decimation) removes quantization noise outside the blue region.

The Sigma Delta modulator has the added feature of noise shaping as shown in diagram C. The quantization noise of the analog to digital conversion is shaped by the modulation scheme shifting it (typically) from a low bandwidth up to a higher frequency allowing a low-pass digital filter to eliminate it from the conversion result. The Sigma Delta ADC can be designed with the noise floor determined by thermal noise and not limited by quantization noise.

Sigma Delta ADC Sampling

The Sigma Delta ADC is clocked using either an internal or external sampling clock. Often the ADC’s master clock (“MCLK”) is divided down prior to use by the modulator - be mindful of this when reading the ADC datasheet and understand the modulator frequency. The sampling frequency passed to the modulator, sets the sampling frequency FMOD. The modulator outputs data to the digital filter at this rate, in turn the digital filter (typically low pass, with some decimation) provides data at the output data rate (ODR). Figure 3 illustrates this flow.


Figure 3. Sigma Delta ADC Flow: Sampling to Modulator output to digitally filtered output.

In depth view of a First Order Sigma Delta Modulator (MOD1)

The sigma delta modulator is a negative feedback system, analogous to a closed loop amplifier. The loop contains a low resolution ADC and DAC, as well as a loop filter. The output and feedback are coarsely quantized often only a single bit output as a high or low. The basic structure is implemented as an analog system for ADCs, where the quantizer is the block in which the sampling is accomplished. Provided conditions exist for stability of the loop, the output is a coarse representation of the input. The digital filter takes the coarse output and reconstructs an accurate digital version of the analog input.


Figure 4. Sigma Delta “One’s Density” in response to Sine wave input. Linear Model (a) of the MOD1 Sigma Delta Loop.

A ones’ density output in response to a sine wave input is illustrated in Figure 4. The rate of change of the modulator output from a low level to high level depends on the rate of change of the input. At full scale input of the sine wave the modulator output switching rate reduces and the output a +1 state dominates, similarly when the sine wave is at its negative full scale, the transitions between + 1 and -1 are reduced and the -1 output dominates. At the maximum rate of change of the sine wave input the highest density of the switching between +1 and -1 in the modulator output occurs. The rate of change of the output is following that of the input. It is the rate of transition of the Sigma Delta Modulator output which describes the analog input.

Using a linear model to describe this Single bit modulator “MOD1” the system is shown as a control system with negative feedback. The quantisation noise is the difference between the input and the output of the quantizer. A low pass filter follows the input “delta” node. In Figure 5 the linear model (b) the quantization noise is described by the term “N”.


Figure 5. Linear Model (b) of the MOD1 Sigma Delta Loop including equations, and filter, signal and noise transfer function plots.

Loop Filter Design

H(f) is the function of the loop filter and it defines both the noise and signal transfer functions. H(f) is a low pass filter function with very high gain at low frequencies (within the bandwidth of interest) and attenuation of higher frequency signals. The loop filter can be implemented as a simple integrator or a cascade of integrators. In practice a DAC is placed in the feedback path to take the digital output signal and feed it back to the analog input “delta” node.

Solving the equations shown in Figure 5 gives the signal and noise transfer functions .The signal transfer function operates as a low pass filter, with a gain of 1 in the bandwidth of interest. The noise transfer function is a high pass filter function, providing the noise shaping. There is strong suppression of the quantization noise at low frequencies around DC. The quantization noise signal seen at high frequencies outside the bandwidth of interest is increased. For the single order modulator (MOD1) the noise increases at a rate of approximately 20dB/decade.

A common method to increase the resolution of the system is to increase the loop filter order by cascading two loop filters. The H(f) of the overall loop filter now has a greater roll off, and the noise transfer function has a transition of 40dB/decade for a MOD2 style. The quantization noise is shaped more aggressively, with much less low frequency noise. Figure 6 compares MOD1 and MOD2 Sigma Delta ADCs.


Figure 6. MOD1, MOD2 block diagram configurations with comparative plots of the filter and noise transfer functions.

Multi-Stage Noise Shaping Modulators (MASH) Architectures

The variations and styles of sigma delta modulators are wide ranging. Architectures which circumvent stability concerns of higher order single bit loops are called Multi-stage noise shaping modulators (MASH) architectures. The multi-stage (MASH style) architectures enable design of stable high order sigma delta modulators through a combination of inherently stable lower order loops.

Moving on from the theory we can look at analysis through the lens of a real ADC. The AD7175 is the latest family of precision sigma delta ADC converters from Analog Devices. The ADC is the first converter on the market to provide a true 24-bit noise free output. The ADC maximizes dynamic range for designers of critically noise sensitive instrumentation circuits, enabling reduction or elimination of preceding amplifier gain in signal conditioning stages. The device can also run at high speed and offer lower settling times than before. This improves the response times to a stimulus on the input in control loops or increases the density of channels that can be converted all with a faster throughput per channel.

All of this comes with a fully integrated analog signal chain with true rail to rail analog input and reference input buffers. The family offers multiple input channel counts with pin-pin upgrades for either speed of conversion or for lower noise or lower power alternatives. AD7175-2 and -8 provide the fastest outputs and lowest noise. AD7177-2 offers a 32-bit resolution output. AD7172 and AD7173 provide the lowest power options.

The AD7175-2 includes an extremely useful software tool to help with its evaluation. EVAL+ is a single piece of software downloadable from the ADI website which can be used to configure, analyze and select the ADC with or without hardware. The software, running with hardware will operate as per the standard evaluation board. Without hardware a functional model of the ADC runs in the background allowing the user to establish the best operating configuration for their end application.

Figure 7. AD7175 Sigma Delta ADC Family, AD7175-2 Block diagram & Noise Performance.


Figure 8. AD7175 Sigma Delta ADC Family Overview.

Eliminating Quantization Noise of Sigma Delta ADCs

The AD7175 ADC will be used to illustrate how the quantization noise of Sigma Delta ADCs can be eliminated using digital filtering. Tradeoffs in noise/input bandwidth and settling time come into focus.

Figure 9 shows the raw modulator noise plotted from versus the log of frequency for AD7175 device from DC to FMOD/2 (or 4MHz). The AD7175 Modulator samples at an effective rate of 8MHz (FMOD). The modulator is a MASH style which is designed to give an 80dB/decade slope to the modulator noise. Thermal noise of the circuit sets the in-band noise floor, before getting to the point of the frequency axis where the modulator noise begins to ramp. This plot illustrating the low noise floor gives an insight into the high dynamic range capability of the ADC for low bandwidth signals. This dynamic range and the ability of the AD7175 to push this noise floor down, translates into improved sensitivity for the user, particularly useful when acquiring low amplitude signals in the application.

ADC Oversampling

The minimum oversampling ratio of the ADC and the digital filter order and corner frequency all contribute to ensuring that the quantization noise is not the limiting factor for the ADC noise. To filter the noise, the envelope of the filter needs to be able to attenuate sufficiently and have sufficient roll off to deal with the rate of increase of the magnitude quantization noise.

The minimum oversampling ratio of the AD7175 is x32, so given the 8MHz FMOD the maximum output data rate offered is 250 kHz.

The AD7175 offers a number of different filter types selectable by the user. The theory behind the operation of a digital filter operation is described by comparing the Sinc 5 +Sinc1 and Sinc 3 filters in different scenarios.

At a 250kHz ODR the AD7175 “Sinc5 + Sinc1 is configured directly as a Sinc 5 path with a -3dB frequency of ~0.2xODR (50kHz). The Sinc 5 filter has an attenuating envelope of -100dB per decade. It means the Sinc 5 filter attenuation and roll off is more than sufficient to eliminate the modulator noise as shown in Figure 9.


Figure 9. AD7175 Modulator output spectrum DC to FMOD/2 with the Sinc5 + Sinc1, decimate by 32 (effectively a Sinc5 response) overlaid.

In contrast, changing to Sinc 3 at 250 kHz ODR the attenuation and roll off are not sufficient to eliminate the modulator noise. The datasheet noise numbers at 250 kHz and 125kHz ODR show this fact. Only when the data rate is set to 62.5kHz and below does the Sinc 3 response fully filter the quantization noise from the ADC result.

Beyond filtering quantization noise the digital filter can be used to trade off input bandwidth for lower noise. This is done by increasing the decimation rate. In the case of the Sinc 5 + Sinc1 filter increasing the oversampling ratio means that the initial 5th order Sinc filter becomes averaged. The averaging of the initial result enables the user to choose from a range of different output data rates and speed and bandwidth improving noise performance show in Figure 11 by the Sinc5 and subsequent Sinc5 +Sinc1 averages to improve the noise performance. Averaging the Sinc 5 result introduces 1st order notches at the output data rate and multiples of that rate which are compound with the overall Sinc 5 envelope. The notches in the Sinc style filter have traditionally been used to reject interferers at known frequencies by strategically setting the data rate to coincide with the interferer frequency. Classic example of this is in 50 & 60 Hz rejection of the line frequency. 


Figure 10. AD7175-2 Sinc 5 + Sinc 1 filter: Adjusting the input bandwidth by changing the decimation rate of the ADC.


Figure 11. AD7175-2 Sinc 5 + Sinc 1 filter – Noise versus ODR plot.

Basics of the Sinc Filter

The “Sinc” style filter is a moving average filter with a Sin(x)/x profile so is commonly referred to as a Sinc filter. The filter is made up of a series of integrators, a switch which operates as the decimator, followed by a series of differentiators. The filter is a FIR (finite impulse response) style, i.e. there is a known and finite response from the filter to a step change at the input and it exhibits a linear phase response.  The zeros of the filter occur at frequencies of 1/averaging period. At the output data rate and integer multiples of this rate, deep notches occur attenuating signals within the notch.

Figure 12 shows the comparison of the 3rd and 5th order Sinc filters- both running with a decimation rate of 32 for the AD7175. In this case both filters will provide conversion data at an output rate of 250kHz. The order of the filter determines both the roll off and the -3dB frequency. A  SincP filter will sit under a frequency response envelope of –P x 20dB/decade. The steeper roll off gives a lower -3dB frequency. The major tradeoff between different orders of filters is in the settling time of the filter which has different effects on the end measurement application depending on the scenario. 


Figure 12. Frequency domain comparison of the different orders of Sinc filters: Sinc5 versus Sinc 3.

Filter Settling Time

As the digital filter processes a moving average of the data stream from the Sigma Delta modulator there is an associated settling time. The delay is fixed for any FIR filter, but differs for each Sinc filter order. The delay is typically described by two terms; Group Delay and Settling Time. The group delay describes the delay between the analog signal being present at the input to when it is seen at the digital output. For a single tone sine wave it is the time between, for instance, the voltage peak of the sine wave existing at the analog input, to the same peak appearing at the digital output.

The settling time is the full averaging time of the digital filter, if there were a step at the analog input it takes the full settling time of the filter until the data output from the ADC has no correlation with that previous step at the input. Other delays can exist such as computation time of the filter, for AD7175 family the first conversion will have a longer settling time or settling after coming out of standby can also incur a delay due to an initial computation cycle of 1/ODR. Any delays in addition to the settling time of the filter can vary depending on the converter selected, be mindful when reading the ADC datasheets.

The filter settling time effect is best shown by comparing a Single Sigma Delta ADC scenario with that of a multiplexed Sigma Delta ADC. The settling time of the digital filter heavily impacts the rate at which the user can cycle the multiple input channels while keeping each channel result independent.

Digital Filtering and Decimation

Why do you need to wait the full settling time to give an independent result? Let’s look at the digital filtering for a single ADC with a single input source. The data from the modulator Sigma Delta ADC from is passed at a rate of FMOD to the digital filter as described in Figure 3 with each sample passed through the moving average filter. Depending on the order and style, the filter weights each sample differently over the conversion time period (set by the filter decimation rate) as shown in Figure 13. Input Sample 0 and subsequent samples are discrete modulator output results, separated by a single period of the modulator clock. The y-axis scales the weighting attributed by the digital filter to each sample. The shape of this weighting is the time domain representation of the low pass digital filter. The output data rate of this situation is 250kHz (8MHz/32= FMOD/Decimation Rate). The time between the data ready signals (vertical lines in each of the different colours) is 4us. The ADC is set up to run with the Sinc5 + Sinc1 filter with a decimation rate of 32. All five conversion outputs have some overlap in the modulator inputs which define the filter output, thus none are independent from each other. For a single ADC input, each conversion result shares inputs from the modulator but the filter weights each of these modulator outputs differently.


Figure 13. Single ADC input, Sinc 5, 5 conversion output cycles.

For the multiplexed input case the modulator data provided to create each conversion output must be independent for each channel. The full settling time of the filter must elapse before the multiplexer switches from one analog input channel to the next. Taking an example of the Sinc 3 style filter, using a decimation rate of 32, the filter settling time is illustrated for one conversion in Figure 14 (A). The data output once the filter is fully settled is a weighted average of the previous 96 outputs from the modulator. This equates to 12us or 3 cycles of the output data rate of the ADC.

Figure 14. Multiplexed ADC, Sinc 3 filter, 3 conversion cycles. Fully settled data.

Figure 14 (B) shows the first 3 samples of the multiplexed situation where each of the samples output by the ADC is fully settled. The modulator output does not overlap between any of the samples. The multiplexed rate indicated by the time between the DRDY (vertical lines) is decided by the settling time of the filter. This rate is often described in datasheets and parametric plots as the “Fully settled data rate”.

For the SincP filter the settling time of the filter is the filter order P, multiplied by 1/ODR. For a Sinc 3 filter running at 250kHz ODR it means that the settling time of the filter is 3x1/250k = 12us. By comparison if using a Sinc 5 filter at the same ODR of 250kHz the settling time of the filter is 5x(1/250k) = 20us.

An approximate rate for switching between channels is the ODR divided by the order of the filter, so ODR/3 for Sinc 3, or ODR/5 for Sinc 5 filter. It is straight forward for direct Sinc filters. An added step is required for cases such as the Sinc 5 + Sinc1 style. The AD7175 family of ADCs offers the ability to choose between different styles of filters. The next section demonstrates the differences between the filter types and also provides an example of calculating the settling time for each of the cases.

Calculating the Settling Time for Different Types of Filters

Let’s work out the settling time and also look at how this relates to the per channel data rate in a multiplexed situation a typical scenario in voltage input, analog input modules for process control, where a preceding attenuation stage scales the +/-10V input to within the input range of the AD7175-8 and multiple inputs of 4 channels or 8 channels are multiplexed through the AD7175-8.

(A)   AD7175 Sinc 3 : ODR= 62.5kHz

Settling time = 3x (1/62.5k) = 48us, Channel Switch Rate= 1/48us = 20.833kHz

(B)   AD7175 Sinc 5 + Sinc 1: ODR = 62.5kHz

Note: There are two components. The Sinc 5 filter averages over a 4us window (FMOD=8MHz) so passes data to the averaging block at a rate of 250kHz.

1)      Settling time of the Sinc 5 = 5x1/250k = 20us

This provides the first sample for the averaging.

2)      Settling for the Sinc1, averaging filter.

For ODR = 62.5kHz, 250kHz data stream is averaged 4 times.

Settling time for the remaining 3 samples for averaging is 3x1/250k = 12us

Total settling time = 20us + 12us =32us, Channel switch rate= 1/32us = 31.25kHz

(Note that for the Sinc5 + Sinc1 filter, at data rates of 10ksps and below the ADC has single cycle settling. This means that the settling time of the ADC = 1/ODR.)

Table 1. Shows the comparison of a 4 channel multiplexed measurement with set up (A) and (B). Using the Sinc 5 +Sinc1 filter enables a faster per channel sampling rate, showing the advantages of shorter settling time. Note that this rule of thumb is relevant to the converter alone, if there are analog preconditioning circuits prior to each input which have longer time constants than that of the ADC, it will be the worst case settling time which will dominate.

This comparison is shown in Table 1.

0516 ADI Behind the Sigma Delta ADC Topology Image 15

Table 1. Per channel data rate comparisons of Sinc5 + Sinc 1 versus Sinc 3 filter for a 4-Channel Multiplexed System (for instance using the AD7175-8)

That completes the overview of Sigma Delta ADCs – the theory surrounding the modulator and concept followed by the examples of the digital filtering, and their effects on noise, settling time and the knock on effects of both within your measurement system. To finish it is needed to acknowledge the content, contribution and influence of Adrian Sherry, Colin Lyden and Walt Kester of Analog Devices to this article.

This article was provided by Analog Devices.

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