HSC-ADC-EVALCZ, High Speed Converter Evaluation Platform Supports multiple ADC channels up to 18 bits

说明

• HSC-ADC-EVALCZ, High Speed Converter Evaluation Platform includes the latest version of Visual Analog and an FPGA-based buffer memory board to capture blocks of digital data from high speed analog-to-digital converter (ADC) evaluation boards. The ADC capture board is connected to the PC through a USB port and is used with Visual Analog to quickly evaluate the performance of high speed ADCs. Users can view an FFT for a specific analog input and encode rate to analyze SNR, SINAD, SFDR and harmonic information. The system can acquire digital data at speeds up to 644 MSPS single data rate (SDR) and 800 MSPS double data rate (DDR). The FPGA contains an integrated FIFO memory that allows capture of data record lengths up to a total of 64 kB