Microchip TechnologyPIC64GX1000-V/FCSMicroprocessore

The PIC64GX1000 RISC-V MPU is a highly power-efficient 64-bit Linux® capable processor, innovative, embedded compute platform based on the RISC-V ISA. The RISC-V CPU micro-architecture implementation is a simple, 5-stage single issue, in-order pipeline that does not suffer from the Meltdown and Spectre exploits found in common out-of-order machines. It has five RISC-V cores which are coherent with the memory subsystem allowing a versatile mix of deterministic real-time systems and Linux in a single, multi-core processor cluster. With Secure Boot built-in, innovative Linux and Real Time modes, a large flexible L2 memory subsystem, and a rich set of embedded peripherals. RISC-V MPU provides embedded developers new choices in secure, power-efficient, embedded compute platforms.

CURIOSITY-PIC64GX1000-KIT-ES DevKit

Features:

• The PIC64GX1000 RISC-V MPU supports the following features:
• •  Quad 600 MHz RV64GC RISC-V application cores (U54)
• •  Physical Memory Protection (PMP) Unit
• •  Memory Management Unit
• •  L1 memory subsystem with single-error correct, double-error detect (SECDED)
• •  32 KB 8-way instruction cache or optional 28 KB tightly integrated memory
• •  32 KB 8-way data cache
• •  Single 600 MHz 64-bit RV64IMAC monitor processor core
• •  16 KB memory subsystem with SECDED configurable as 2-way L1 instruction cache or as an instruction tightly integrated memory
• •  8 KB data tightly integrated memory
• •  PMP unit
• •  Flexible 2 MB L2 memory subsystem with SECDED configurable as:
• •  16-way set associative L2 cache
• •  Loosely Integrated Memory (LIM) mode for deterministic access
• •  Coherent Scratchpad Memory mode for shared messages across cores
• •  Integrated 36-bit DDR4/LPDDR4 memory controller with SECDED
• •  DDR4 at 1.6 Gbps with a 8 Gb address reach
• •  Cache coherent CPU bus matrix
• •  AMBA I/O switch with QoS and memory protection
• •  Integrated 128 Kbytes embedded non-volatile memory (eNVM) for boot
• •  Boot options
• •  Microchip secure boot
• •  User defined, PUF-protected secure boot
• •  Boot directly from 128 KB eNVM
• •  Platform interrupt controller
• •  48 interrupt sources, with seven priority levels per core
• •  Debug
• •  Ten hardware triggers per CPU (triggers can be configured as a breakpoint or a watchpoint)
• •  Performance counters
• •  Processor I/O
• •  Two GigE MACs
• •  A USB 2.0 OTG
• •  MMC 5.1 SD/SDIO
• •  Two CAN 2.0 A and B
• •  Execute in place Quad SPI flash controller
• •  Five multi-mode UARTs
• •  Two SPI, two I2C
• •  HDMI® 1.4
• •  MIPI® CSI-2
• •  RTC, GPIO
• •  Five watchdog timers
• •  Timers
• •  Integrated x4 PCIe® Gen 2
• •  1.05V operating mode
• •  Security Features
• •  Use cryptoprocessor
• •  Athena F5200 TeraFire Crypto Processor (1x), 200 MHz
• •  Integrated dual physically unclonable function (PUF)
• •  56 Kbytes of secure, non-volatile memory (sNVM)
• •  Built-in tamper detectors and countermeasures
• •  Digest integrity check for sNVM, and eNVM
• •  Junction Temperature (TJ) Range
• •  Industrial: -40 °C to +100 °C
• •  Extended Commercial Temperature Range: 0 °C to +100 °C
• •  Packages
• •  FCSG325 (11 mm x 11 mm)
• •  FCVG484 (19 mm x 19 mm)

Applications

• •  Automatic test equipment
• •  Avionics and aerospace
• •  Instrumentation and control systems
• •  Semiconductor manufacturing
• •  Test and measurement