Accelerate the Design of Cost Sensitive IoT Devices

Altera’s low-cost MAX® 10 FPGAs capture the advantages of CPLDs and FPGAs in a single package. Building on the best of both worlds, MAX 10 FPGAs enable the next level of cost effective integration – the perfect core for any smart device connected to the cloud.

Packed with sophisticated features and optimized to implement embedded products efficiently, MAX 10 FPGAs are simple to use. Building a MAX 10 application is easy thanks to the Altera’s versatile development kits, example designs, and a strong user community.

MAX 10 FPGAs reduce cost and size with:

  • - Internal flash for non-volatile storage of bit stream and user data.

  • - A 32-bit Nios® II soft processor eliminates the need for a separate processor.

  • - Remote upgrade capability eliminates the need for a separate configuration controller.

  • - Internal PLLs for sophisticated clock management

  • - A single power supply option reduces PCB board layers and the need for multiple regulators.

  • - An integrated multichannel, 12-bit SAR ADC removes the requirement for an external analog to digital converter.

  • - An integrated temperature sensing diode eliminates the need for a separate temperature sensor.

  • - A versatile I/O ring reduces voltage level translator and passive component requirements.

See related product

DECA

Arrow Development Tools Programmable Logic Development Boards and Kits View

A significant advantage for MAX 10 FPGAs is internal flash memory, and Altera has included a number of features that make the internal flash even more useful. FPGAs typically require power up time to read the configuration image from external memory. MAX 10 FPGAs feature instant power up from one of several internal configuration flash arrays that provide a dynamic fail-safe remote upgrade. You can enable a watchdog timer to monitor remote flash configuration with automatic fall back to a previous image if configuration is unsuccessful. Additionally, multiple integrated flash arrays provide program and data storage, eliminating the need for external, non-volatile memory in many applications. 


  • MAX 10 FPGAs incorporate an integrated voltage regulator, which reduces power supply cost and size with a single 3.0 - 3.3 V power supply option. A high efficiency dual-supply device option is also available. The versatile I/O ring supports a variety of single and differential I/O standards, including 3.3-V LVTTL/LVCMOS. When combined with independent I/O bank voltage capability, you can avoid separate level translating buffers. Every I/O element can optionally configure a Schmitt trigger input buffer to provide noise immunity and switch debouncing. Each I/O element contains two output enabled registers that can operate in DDR mode for high-speed serial bus and memory interfaces. Open-drain capable outputs with optional internal pull-up resistors with a configurable slew rate control and a programmable current strength can drive up to 16 mA for some interface standards.


  • Analog blocks containing multichannel ADCs, a temperature sensing diode and an integrated 116-MHz internal ring oscillator round off this powerful architecture. Combined with a PWM or delta sigma converters and Altera’s DSP Builder, you can use MAX 10 FPGAs at the heart of monitoring and control applications that require ADC conversion and signal processing. With TMSC’s 55 nm NOR flash technology, Altera’s rich collection of intellectual property, and a powerful development ecosystem, designers have ready access to the device’s flexible FPGA fabric. This fabric incorporates DSP blocks, LPDDR2/DDR3 interface capability, PLLs, up to 50K logic elements (LEs), and 1.6Mbits of block RAM. Central to Altera’s easy to use IP portfolio is the Qsys system integration tool, which enables developers to define a system architecture that instantiates a wide variety of interoperable soft-core modules.


  • View Larger

  • Figure 1 Qsys Development Environment (View Larger)

  • This portfolio includes the world’s most versatile embedded processor – the 32-bit Nios II processor. The NIOS II processor can operate at up to 130MHz for the fast core, a large user community and comprehensive operating system support.

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 Figure 2: Nios II Processor Architecture and OS Support

Get Started Immediately with a Development Kit

Developments kits simplify the design process, enabling rapid FPGA design development and embedded software on a well-documented reference platform. Many kits are available, and are optimized for a wide range of applications. Basing an underlying hardware architecture on tried and tested reference design elements lets you use working example projects as starting points–speeding development and mitigating risk. Accelerate your development time by combining this strategy with a wide variety of available operating systems with development kit specific BSPs, integrated networking stacks, and device drivers.


The Terasic Nios II Embedded Development Kit (NEEK) has everything required to create a full processor-based system. It is an integrated platform with a number of reference designs that focus on a range of applications. The kit is optimized to enable rapid design of customized solutions for embedded processing applications, multimedia interface products, human-machine interfaces, and video display. The kit features a capacitive LCD multimedia color touch panel with native support for multi-touch gesturing. It also incorporates an eight megapixel image sensor, a light sensor, and a three-axis accelerometer. Demonstration reference designs include robotic control, HDMI Rx, sensing, audio, and camera interfacing.

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Figure 3: Terasic MAX 10 Nios II Embedded Development Kit

The Altera MAX 10 FPGA Development Kit is optimized for a wide variety of applications including HDMI and industrial Ethernet designs. An embedded Linux reference design is available for the Nios II processor, and features strong online community support. The development kit includes interfaces to daughter cards and peripherals using HSMC and Digilent Pmod™ compatible connectors, and has built-in FPGA power monitoring using the power monitor graphical user interface (GUI). The board is well documented, open, and reusable as a proven platform to base a design upon.

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Figure 4: Altera MAX 10 FPGA Development Kit

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Figure 5: Altera MAX 10 FPGA Development Kit Architecture

The MAX 10 FPGA Evaluation Kit  is a low-cost, entry-level board with integrated FPGA power supply monitoring and an adjustable I/O bank voltage to enable level translation. The board features an Altera Enpiron power supply and enables access to the FPGA’s flash memory, ADC interfaces, and the digital I/O ring. The kit is incredibly flexible due to an integrated Arduino UNO R3 interface connector that enables connection to compatible Arduino Shields. This feature enables thousands of peripheral boards containing functionality such as sensors, motor controllers, GPS, and wireless transceivers. The kit’s PCB board and schematic are well documented and available as a model for designs.

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Figure 6: MAX 10 FPGA Evaluation Board

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Figure 7: MAX 10 FPGA Evaluation Board Architecture

The BeMicro MAX 10 development kit, available from Arrow, enables designers to evaluate and utilize the MAX 10 FPGA for embedded applications. It includes an Enpiron power SoC, 8 Mbytes of SDRAM, an accelerometer, LEDs, pushbuttons, and expansion connectivity. The expansion headers include two 6-pin Digilent Pmod™ connectors and two 4-pin prototyping headers along with an 80-pin card edge connector. Users can directly interface development tools via the built-in USB-Blaster port. The board is well documented with a Getting Started User Guide for accelerating designs, and is a perfect low-cost prototyping platform for rapid development.

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Figure 8: BeMicro MAX 10

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Figure 9: BeMicro MAX 10 Architecture

See related product

BEMICROMAX10

Arrow Development Tools Programmable Logic Development Boards and Kits View

Arrow’s small DECA MAX 10 Development Board  is a powerful, highly versatile and robust development platform. It incorporates DDR3 memory, Ethernet, gesture light sensing, HDMI TX, audio line in or out, microSD socket, and two SMA inputs for the MAX 10 ADCs. The DECA system comes complete with a BYD camera and WiFi-BLE wireless interface modules that plug into the board’s two 46-pin Beagle Bone Black (BBB) expansion headers. Developers can use Arrow’s BLE/WIFI BeagleBone compatible cape that showcases Texas Instrument’s families of BLE and Wi-Fi solutions. Developers can also use the camera module to capture 8 megapixel CMOS images using a MIPI video input interface.

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Figure 10: DECA MAX 10 Development Board

Try It Today!

Developing a system based upon an embedded FPGA has never been simpler. MAX 10 FPGAs offer integration levels that truly enable significant cost savings. A variety of development kits with operating system BSP support and access to peripheral expansion for sensing and network connectivity enable MAX 10 FPGAs in applications that previously required more complex and expensive microcontrollers. The introduction of dynamic image and user flash uploading via a UART interface with a watchdog and failsafe fall back future-proofs designs by facilitating upgrades and support. Hardware development risk is mitigated through well documented robust solutions, and software is accelerated with reference designs and a strong user community. FPGA design tools also include free web-based options. Software development and debugging is easy with Altera’s Eclipse-based software development environment. Talk to an Altera representative about how they can get you started today!




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