Altera SoC Roadmap Drives Improved Efficiency

Electronics system designers are faced with a bewildering set of requirements from their customers. Their customers want increased system performance but don’t want an increase in power. They also expect new features and capabilities but don't want extended waits for these new capabilities to become available. SoC FPGAs have been helping system designers unravel this knot of their conflicting customer demands by continually improving performance and features without sacrificing low power or fast time to market. In particular, the Altera SoC FPGA Families- Cyclone V, Arria V, Arria 10 and Stratix 10 cover a wide range of applications from low-cost to high-end.

Figure 1 below shows the wide range of capabilities Altera’s SoC FPGAs have and key features for each device families. The capabilities of the processors, transceivers, DDR memory interfaces, number of logic elements and multiplier have been optimized for the key applications within each of the three market segments. 

0716 Altera SoC Roadmap Drives Improved Efficiency Image 1
 
Figure 1: Altera SoC FPGA Roadmap Covers Applications from Low-Cost to High-End and Everything In-Between

Why Consider using an SoC FPGA?

You may be wondering why you might consider using an SoC FPGA in your design when you already have a multitude of devices choices available to you. Consider these following situations however where an SoC FPGA might be an excellent fit.

• If you have an external processor already sitting next to an FPGA on your circuit board, might an SoC FPGA with the processor integrated on-chip be a better solution?

• If you have a DSP and an FPGA on the same circuit board might an SoC FPGA with a hundreds of dedicated multipliers and a hardened processor be a better solution?

• If you have an algorithm that can be implemented more efficiently in hardware, might an SoC FPGA with customized hardware acceleration be a better solution?

• If you need to customize an interface would an SoC FPGA with flexible high performance interfaces interface be a good fit?

• If memory bandwidth is important SoC FPGAs can implement very high-speed off-chip memory interfaces and with hundreds of on-chip buffer memories can make sure on-chip processing makes the most use of all the available memory bandwidth.  

• If you are working on an evolving industry standard an SoC FPGA allows you to make hardware changes, even after equipment has been shipped and installed- isn't that an ideal solution?

• If you have a range of products with different performance, cost and power points SoC FPGA offer a wide range of capabilities from low cost to high performance without changing tools, development methodologies or deployment and update methodologies.

Altera SoC FPGAs- Cover Your Application Requirements

Altera SoC FPGAs cover a wide range of target applications and market segments. Let’s look at the three main segments, shown in Figure 1, in more detail to better understand their key differences.

Low Cost SoC FPGAs

For differentiated high volume applications such as industrial motor control drives, protocol bridging, video converter and capture cards, and handheld devices Altera's Cyclone® V SoCs provide the industry's lowest system cost and power. Devices come in a wide range of programmable logic densities with many system-level functions hardened in silicon making these functions intrinsically low power and low cost. Some of the key features of Cyclone V devices that address low cost, high volume system requirements include:

• Single or dual-core ARM® Cortex®-A9 hard processor system (HPS)
• Hardened multi-port memory controller that supports cost effective DDR3 and low power LPDDR2 memories
• Embedded memory interfaces for QSPI, SD/SDIO/MMC, NAND
• Embedded, cost effective and low power peripherals for Ethernet MAC, PCI Express®, USB, UART, SPI, I2C and CAN

Midrange SoC FPGAs

For mid-range applications Altera provides two SoC FPGA families. The 28 nm Arria V SoC FPGA offer high performance with the lowest total power and the 20 nm Arria 10 SoC FPGA improves performance over the Arria V without sacrificing power efficiency. 

28 nm Arria V

The Arria V Family targets mid-range applications such as remote radio units, 10G/40G line cards, medical imaging, and broadcast studio equipment. The chip diagram for an Arria V devices is shown in Figure 2, below. It includes a hard processor system (HPS) consisting of a dual-core ARM® Cortex™-A9 processor and dedicated peripherals for efficient high speed processing. Flexible memory interfaces provide significant off chip bandwidth to support complex on-chip processing functions. High speed serial interfaces support up to 2x 10/00/1000 Ethernet MACs.

  0716 Altera SoC Roadmap Drives Improved Efficiency Image 2
Figure 2: Arria V Chip Diagram- Integration and Flexibility

20 nm Arria 10

The Arria 10 SoC Family pushes performance without sacrificing power efficiency or features. Target applications for Arria 10 wireless infrastructure, compute and storage equipment, broadcast studio and distribution, wireline 100G aggregation and bridges and digital medical diagnostic equipment. Arria 10 delivers the following improvements in performance and power reduction when compared to the previous Arria V SoC family:
• 87% higher processor performance with up to 1.5 GHz CPU operation per core
• 60% higher performance versus the previous generation, over 500 MHz-capable FPGA logic core performance (15% higher performance than previous SoC)
• 4X more transceiver bandwidth versus the previous generation 
• 4X higher system performance (2,400 Mbps DDR4 SDRAM, Hybrid Memory Cube support)
• More than 1,500 giga floating-point operation per second (GFLOPs) and up to 50 GFLOPs per Watt in a single device
• 40% lower power with process technology improvement and innovative techniques for power reduction

High End SoC FPGAs

For high end next generation applications for communications, data center aggregation, high performance computing, radar processing, and ASIC prototyping the Altera Stratix® 10 SoCs deliver breakthrough advantages in performance, power efficiency, density, and system integration. Implemented in the Intel 14 nm Tri-Gate process and using the revolutionary HyperFlex™ core fabric architecture these devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power. Some of the key features of Stratix 10 devices that address high-performance system requirements include:

• Integrated quad-core 64 bit ARM® Cortex®-A53 hard processor system up to 1.5 GHz
• Heterogeneous 3D System-in-Package (SiP) integration
• Highest memory bandwidth with HBM2 DRAM integrated in-package
• The highest density FPGA fabric with up to 5.5 million logic elements (LE) 
• Up to 10 Tera floating point operations per second (TFLOPS) of IEEE 754 compliant single precision floating-point digital signal processing (DSP) throughput

An example solution for wireline bridging and aggregation is show in the figure below. Four 100G Ethernet ports are managed and bridged to a 500G Interlaken interface. Up to 600 million packet per second transfer throughput is supported at less than 1 watt per 10 Gbps. The HyperFlex architecture places massive register resources within the routing fabric to dramatically cut routing delays. This makes it possible to achieve an operating frequency of over 700 MHz using a 512 bit wide data path- twice the performance of other implementations. This combination of high speed and wide data path cuts the logic required to implement the IP by up to 50%, reducing system cost and overall power requirements. dissipation.

  0716 Altera SoC Roadmap Drives Improved Efficiency Image 3
Figure 3: Bridging and Aggregation Application

The integrated ARM processor is a quad core implementation with a 1MB L2 cache that provides continuous high performance. It is ideal for managing traffic, setting up the scheduler, and adapting to varying loads. Processors can be enabled or disabled as needed which helps reduce average power requirements without sacrificing overall performance.

Putting Altera SoC FPGAs to Work
To quickly come up to speed on the capabilities of these device families you can purchase a development kit, download the software and try out some example designs. Here are some suggested kits, available from Arrow, to get you started:

For the Arria V try this kit: https://www.arrow.com/en/products/arriavrfdevkit/texas-instruments

In addition to learning hands-on with a kit and example designs you can consider the  Altera On-line and Instructor led training. These courses coverall aspects of SOC design from creating your first project to developing, testing and debugging a processor based example system. 

Putting Arrow to Work

Don’t forget to put Arrow through their paces too. The Arrow SoC Center of Excellence is staffed with teams of engineers who work behind the scenes to support all aspects of SoC designs. From device selection, to IP implementation trade-offs to development kit tricks and techniques the Arrow SoC Center of Excellence does it all. 

Conclusion

As system requirements become more and more challenging the odds are good that an Altera SoC is going to show up in one of your designs. Get started now and get a head start on your competition.

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