Analog DevicesEVAL-ADF4007EBZ1时钟和计时开发板和套件
ADF4007 Clock Generator and Synthesizer Evaluation Board
| Compliant | |
| 5A991b. | |
| Active | |
| 8473.30.11.80 | |
| Automotive | No |
| PPAP | No |
| Evaluation Board | |
| ADF4007 | |
| Clock Generator and Synthesizer | |
| 15 |
Dev Kit Description
This board is designed to allow the user to evaluate the performance of the ADF4007 frequency synthesizer for PLLsphase locked loops). The block diagram of the board is shown in Figure 1. It contains the ADF4007 synthesizer, links for choosing the divide ratio (8, 16, 32, and 64), an SMA connector for the reference input, and an RF input and output.
| EDA / CAD Models |
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