Complex Programmable Logic Devices - CPLDs

5M80ZE64I5N

CPLD MAX® VFamily 64Macro Cells 118.3MHz 1.8V 64-Pin EQFP EP Tray

Altera

製品技術仕様

• RoHS (Unione Europea)

  Compliant

• ECCN (Stati Uniti)

  EAR99

• Stato del componente

  Active

• Codice HTS

  COMPONENTS

• Automotive

  No

• PPAP

  No

• Family Name

  MAX® V

• Logic Elements

  80

• Program Memory Type

  Flash

• Memory Size (Kbit)

  8

• Number of Logic Blocks/Elements

  24

• Number of Global Clocks

  4

• Number of I/O Banks

  2

• Number of Macro Cells

  64

• Data Gate

  No

• Maximum Number of User I/Os

  54

• In-System Programmability

  Yes

• Programmability

  Yes

• Reprogrammability Support

  Yes

• Maximum Internal Frequency (MHz)

  1474.9

• Maximum Internal Frequency (MHz)

  118.3

• Maximum Clock to Output Delay (ns)

  8.6

• Maximum Propagation Delay Time (ns)

  14|8.5

• Speed Grade

  5

• Individual Output Enable Control

  Yes

• Minimum Operating Supply Voltage (V)

  1.71

• Maximum Operating Supply Voltage (V)

  1.89

• Typical Operating Supply Voltage (V)

  1.8

• I/O Voltage (V)

  1.5|1.8|2.5|3.3|1.2

• Tolerant Configuration Interface Voltage (V)

  5

• Minimum Operating Temperature (°C)

  -40

• Maximum Operating Temperature (°C)

  100

• Supplier Temperature Grade

  Industrial

• Packaging

  Tray

• Tradename

  MAX

• Mounting

  Surface Mount

• Package Height

  1

• Package Width

  7

• Package Length

  7

• PCB changed

  64

• Standard Package Name

  QFP

• Supplier Package

  EQFP EP

• Pin Count

  64

• Lead Shape

  Gull-wing