複雑なプログラマブルロジックデバイス - CPLDs

5M1270ZT144C4N

CPLD MAX® VFamily 980Macro Cells 247.5MHz 1.8V 144-Pin TQFP Tray

Altera

製品技術仕様

• EU RoHS

  Compliant

• ECCN (US)

  EAR99

• Part Status

  Active

• HTS

  COMPONENTS

• Automotive

  No

• PPAP

  No

• Family Name

  MAX® V

• Logic Elements

  1270

• Program Memory Type

  Flash

• Memory Size (Kbit)

  8

• Number of Logic Blocks/Elements

  221

• Number of Global Clocks

  4

• Number of I/O Banks

  4

• Number of Macro Cells

  980

• Data Gate

  No

• Maximum Number of User I/Os

  114

• In-System Programmability

  Yes

• Programmability

  Yes

• Reprogrammability Support

  Yes

• Maximum Internal Frequency (MHz)

  247.5

• Maximum Clock to Output Delay (ns)

  5.9

• Maximum Propagation Delay Time (ns)

  8.1, 4.8

• Speed Grade

  4

• Individual Output Enable Control

  Yes

• Minimum Operating Supply Voltage (V)

  1.71

• Maximum Operating Supply Voltage (V)

  1.89

• Typical Operating Supply Voltage (V)

  1.8

• I/O Voltage (V)

  1.2, 1.5, 1.8, 2.5, 3.3

• Tolerant Configuration Interface Voltage (V)

  5

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  85

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  MAX

• Mounting

  Surface Mount

• Package Height

  1.4

• Package Width

  20

• Package Length

  20

• PCB changed

  144

• Standard Package Name

  QFP

• Supplier Package

  TQFP

• Pin Count

  144

• Lead Shape

  Gull-wing