ADRV9022: Integrated, Quad RF Transceiver with Observation Path

The receiver subsystem consists of four wide-bandwidth, direct conversion receivers with excellent dynamic range. The transmitters use direct conversion modulation, enabling low-noise operation and power efficiency. Two wide-bandwidth, time-shared observation receivers with dual inputs monitor the transmitter outputs.
 
The transceiver integrates automatic and manual attenuation control, DC offset correction, quadrature error correction (QEC), and digital filtering, removing the need for these in the digital baseband. Additional integrated functions include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs and outputs (GPIOs) for flexible digital control.
 
To ensure high RF performance, the device includes five fully integrated phase-locked loops (PLLs). Two for high-performance, low-power, fractional-N RF synthesizers, one for an independent local oscillator (LO) mode for the observation receiver, one for the converter and digital circuits, and one for the serial interface clock.
 
A multichip synchronization mechanism aligns the phase of all LOs and baseband clocks across multiple ADRV9022 devices. All voltage-controlled oscillators (VCOs) and loop filter components are integrated and digitally adjustable.
 
The ADRV9022 supports flexible operation as either a 4T4R transceiver in a single band or two 2T2R transceivers in a separate band, with dual LOs enabling simultaneous multiband operation.
 
The device includes a fully integrated, low-power digital predistortion (DPD) engine for power amplifier linearization, allowing the use of high-efficiency power amplifiers and reducing serialization and deserialization (SERDES) lane requirements. The low-power crest factor reduction (CFR) engine lowers the peak-to-average ratio (PAR), improving transmitter efficiency and easing the baseband processor load.
 
The serial data interface includes four serializer and four deserializer lanes, supporting both JESD204B and JESD204C standards up to 24.33 Gbps. Interleaved mode is supported for lower bandwidths, reducing the number of high-speed lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.
 
The ADRV9022 operates from 1.0 V, 1.3 V, and 1.8 V supplies and is controlled via a standard serial peripheral interface (SPI). Included power-down modes help minimize energy use. The device is packaged in a compact 14 mm × 14 mm, 289-ball chip scale ball grid array (CSP_BGA).

• 4 differential transmitters
• 4 differential receivers
• 2 observation receivers with 2 inputs each
• Single-band 4T4R or dual-band 2T2R operation
• Fully integrated DPD adaptation engine for power amplifier linearization
• Crest factor reduction engine
• LO tuning range: 75 MHz to 6000 MHz
• RF range: 10 MHz to 6100 MHz
• Maximum receiver bandwidth: 200 MHz
• Maximum transmitter large signal bandwidth: 200 MHz
• Maximum transmitter synthesis bandwidth: 450 MHz
• Maximum observation receiver bandwidth: 450 MHz
• Fully integrated independent fractional-N RF synthesizers
• Fully integrated clock synthesizer
• Dual external LO inputs supporting operation up to 6 GHz
• Multichip phase synchronization for all LOs and baseband clocks
• Support for TDD and FDD applications
• 24.33 Gbps JESD204B/JESD204C digital interface
• Simplifying thermal and power consumption challenges
  • 6.89 W power consumption for the TDD mode, DFE enabled use case with 200 MHz occupied bandwidth

• Tactical communications, phased array radar, and electronic warfare
• Wireless test and measurement
• Portable instruments
• TDD and FDD applications