Altera5SGXMA4H2F35I2GField Programmable Gate Arrays - FPGAs
FPGA Stratix® V GXFamily 420000Cells 0.85V Tray
| Compliant | |
| 3A991 | |
| NRND | |
| 8542.31.00.60 | |
| SVHC | Yes |
| Automotive | No |
| PPAP | No |
| Stratix® V GX | |
| 28nm | |
| 552 | |
| 634000 | |
| 0.85 | |
| Utilize Memory | |
| 420000 | |
| 512 (18x18) | |
| SRAM | |
| 37888 | |
| 1900 | |
| 2 | |
| RapidIO to AXI Bridge Controller (RAB)|Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Sub-frame Latency JPEG 2000 Encoder (BA130)|SPAUI MAC|RLDRAM II Controller Core | |
| Altera/Barco Silex/Mobiveil, Inc/Commsonic | |
| 420000 | |
| 24 | |
| 36 | |
| No | |
| 14.1 | |
| 256 | |
| 2 | |
| Yes | |
| Yes | |
| 8 | |
| No | |
| Yes | |
| 2 | |
| LVPECL|LVDS|HCSL | |
| LVTTL|LVCMOS | |
| DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|RLDRAM III|QDRII+SRAM | |
| 0.82 | |
| 0.88 | |
| 1.2|1.25|1.35|1.5|1.8|2.5|3 | |
| -40 | |
| 100 | |
| Industrial | |
| Stratix |
| EDA / CAD Models |
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