AlteraEP3SL340F1760I3G现场可编程门阵列
FPGA Stratix® III LFamily 337500Cells 500MHz 1.1V 1760-Pin FBGA Tray
| Compliant | |
| 3A001.a.7.a | |
| NRND | |
| 8542.31.00.60 | |
| Automotive | No |
| PPAP | No |
| Stratix® III L | |
| 65nm | |
| 1120 | |
| 24 | |
| 1.1 | |
| Utilize Memory | |
| 337500 | |
| 576 (18x18) | |
| SRAM | |
| 18381 | |
| 48+1040+6750 | |
| EtherCAT|EtherNET/IP|DS1/E1 TDM over Packet IP core|Sub-frame Latency JPEG 2000 Encoder (BA130)|RapidIO to AXI Bridge Controller (RAB) | |
| Barco Silex/Mobiveil, Inc | |
| 337500 | |
| 16 | |
| 12 | |
| No | |
| No | |
| Yes | |
| 500 | |
| No | |
| 3 | |
| LVPECL|LVDS | |
| LVTTL|LVCMOS | |
| DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|QDRII+SRAM | |
| 1.05 | |
| 1.15 | |
| 1.2|1.5|1.8|2.5|3.3 | |
| -40 | |
| 100 | |
| Industrial | |
| Stratix | |
| Mounting | Surface Mount |
| Package Height | 2.83 |
| Package Width | 42.5 |
| Package Length | 42.5 |
| PCB changed | 1760 |
| Standard Package Name | BGA |
| Supplier Package | FBGA |
| 1760 | |
| Lead Shape | Ball |
| EDA / CAD Models |
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