AlteraEP2S60F1020I4现场可编程门阵列
FPGA Stratix® IIFamily 60440Cells 711.24MHz 1.2V 1020-Pin FC-FBGA Tray
| Not Compliant | |
| 3A001a.7.a. | |
| Obsolete | |
| 8542.31.00.60 | |
| SVHC | Yes |
| SVHC超标 | Yes |
| Automotive | No |
| PPAP | No |
| Stratix® II | |
| 90nm | |
| 718 | |
| 8 | |
| 1.2 | |
| Utilize Memory | |
| 60440 | |
| 144 (18x18) | |
| SRAM | |
| 2484.6 | |
| 2+255+329 | |
| Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz | |
| Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA | |
| 60440 | |
| 16 | |
| 12 | |
| 36 | |
| No | |
| No | |
| No | |
| 711.24 | |
| Yes | |
| 4 | |
| 37.8 | |
| 37800 | |
| LVPECL|LVDS | |
| LVTTL|CMOS|SSTL|HSTL | |
| 1Gbps | |
| DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM | |
| 1.15 | |
| 1.25 | |
| 1.5|1.8|2.5|3.3 | |
| -40 | |
| 100 | |
| Industrial | |
| Tray | |
| Stratix | |
| Mounting | Surface Mount |
| Package Height | 3(Max) |
| Package Width | 33 |
| Package Length | 33 |
| PCB changed | 1020 |
| Standard Package Name | BGA |
| Supplier Package | FC-FBGA |
| 1020 | |
| Lead Shape | Ball |
| EDA / CAD Models |
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