AlteraEP2S30F672C5现场可编程门阵列
FPGA Stratix® IIFamily 33880Cells 609.76MHz 1.2V 672-Pin FC-FBGA Tray
| Not Compliant | |
| 3A991d. | |
| Obsolete | |
| COMPONENTS | |
| SVHC | Yes |
| SVHC超标 | Yes |
| Automotive | No |
| PPAP | No |
| Stratix® II | |
| 90nm | |
| 500 | |
| 8 | |
| 1.2 | |
| Utilize Memory | |
| 33880 | |
| 64 (18x18) | |
| SRAM | |
| 1337.6 | |
| 1+144+202 | |
| Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz | |
| Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA | |
| 33880 | |
| 16 | |
| 6 | |
| 16 | |
| No | |
| No | |
| No | |
| 609.76 | |
| Yes | |
| 5 | |
| 16.8 | |
| 16800 | |
| LVPECL|LVDS | |
| LVTTL|CMOS|SSTL|HSTL | |
| 1Gbps | |
| DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM | |
| 1.15 | |
| 1.25 | |
| 1.5|1.8|2.5|3.3 | |
| 0 | |
| 85 | |
| Commercial | |
| Tray | |
| Stratix | |
| Mounting | Surface Mount |
| Package Height | 3(Max) |
| Package Width | 27 |
| Package Length | 27 |
| PCB changed | 672 |
| Standard Package Name | BGA |
| Supplier Package | FC-FBGA |
| 672 | |
| Lead Shape | Ball |
| EDA / CAD Models |
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