複雑なプログラマブルロジックデバイス - CPLDs

5962-8946801XC(E2VCYPRESS)

CPLD 2.5KGates 128Macro Cells 33.3MHz 5V 68-Pin PGA

Teledyne e2v Semiconductors

Spécifications techniques du produit

• EU RoHS

  Supplier Unconfirmed

• ECCN (US)

  3A001a.2.c.

• Part Status

  Unconfirmed

• HTS

  COMPONENTS

• Automotive

  No

• PPAP

  No

• Program Memory Type

  EPROM

• Number of Logic Blocks/Elements

  8

• Number of Macro Cells

  128

• Product Terms

  32

• Device System Gates

  2500

• Data Gate

  No

• Maximum Number of User I/Os

  52

• Number of Flip Flops

  128

• In-System Programmability

  No

• Number of Inter Dielectric Layers

  2

• Programmability

  Yes

• Reprogrammability Support

  Yes

• Maximum Internal Frequency (MHz)

  40

• Maximum Internal Frequency (MHz)

  33.3

• Maximum Clock to Output Delay (ns)

  20

• Maximum Propagation Delay Time (ns)

  35

• Speed Grade

  35

• Individual Output Enable Control

  No

• Minimum Operating Supply Voltage (V)

  4.5

• Maximum Operating Supply Voltage (V)

  5.5

• Typical Operating Supply Voltage (V)

  5

• Minimum Operating Temperature (°C)

  -55

• Maximum Operating Temperature (°C)

  125

• Supplier Temperature Grade

  Military

• Mounting

  Through Hole

• PCB changed

  68

• Supplier Package

  PGA

• Pin Count

  68