DSP-driven high-performance clock sources radically alter system timing architectures

Customers are continually demanding more access to low-cost, multi-protocol network devices. While this is great from an ease-of-use perspective, it presents system design challenges at the IC level. In this article, find out how new digital signal processing (DSP) technology is bringing multi-frequency timing capability to modern ICs.

Traditional multi-rate clock solutions

System designers have been able to provide a limited degree of data rate flexibility while still employing existing clock source technology. These designs are typically faced with the challenge of multiplying a low-frequency network synchronization clock up to multiple high-frequency reference clocks as shown in Figure 1. Additionally, the timing subsystem must monitor the health of the network synchronization clocks while providing the capability to hitless switch between input references without causing phase transients on the transmit reference clock.

To further complicate the timing subsystem design, sub-picosecond (RMS) jitter clock requirements necessitate the use of jitter attenuating clock multiplier phase-locked loops (PLLs) of the type commonly constructed using discrete voltage-controlled SAW oscillators (VCSO) devices, phase detectors, and loop filter elements. These PLL designs also need to support non-integer clock multiplication ratios needed for translation between base data rates and FEC line rates.

Digitally-controlled oscillators (DCO)

Recently, integrated circuit (IC) designers have started taking advantage of high-density, high-speed CMOS technology to develop digital signal processing (DSP) intensive clock source solutions that are both high performance and frequency-agile. These DSP-based architectures (see Figure 2) use a low-frequency resonator element (typically a quartz crystal) and a high-frequency on-chip VCO to produce a frequency-agile high-speed, low-jitter output clock whose output rate is digitally-controlled and whose jitter performance equals that of traditional high-performance VCSOs. The resolution of the digital frequency control can be very fine, much less than one ppm, with a continuous tuning range of more than one GHz. Compared to the high frequency (>100 MHz), high absolute accuracy (<±20 ppm) and pulled (±20-100 ppm) resonators required in traditional high-performance VCSOs, these resonators can be tiny and inexpensive because the reference resonator is low frequency (<40 MHz), has loose absolute frequency accuracy requirements (<±10,000 ppm) and is not pulled with changes in DCO output frequency. These resonators can be very small and inexpensive.

New DSP enhanced PLL architecture

Utilizing the digital control interface provided by the DCO, a fully integrated digital PLL becomes possible that takes advantage of digital signal processing (DSP) algorithms as shown in Figure 3. In this DSP-based PLL architecture, the phase detector output is converted to a digital format by a highspeed analog to digital converter (ADC). Following the ADC, all signal processing is done in the digital domain using high-speed DSP algorithms. The wide tuning range of the DCO (~15%) when combined with high-performance output dividers enables one PLL design to support a wide range of clock multiplication factors that would normally require multiple VCSO-based PLLs. In addition, the phase noise performance of the silicon-based DCO is equivalent to that of fixed frequency VCSO alternatives, enabling narrowband loop operation for applications requiring jitter attenuation. The relative phase-noise performance of VCSO-based clock multiplier hybrids and a fully integrated DCO-based clock multiplier is shown in Figure 4. The biggest difference can be seen at high frequencies where the lower thermal noise of CMOS PLL yields improved jitter performance compared to the hybrid approaches.

System-level simplification

The emergence of frequency-agile, high-performance clock sources simplifies the timing subsystem in multi-rate, multi-protocol network interfaces. As an example, the system-level timing architecture for the multi-rate and multiprotocol interface card described above (see Figure 1) can be dramatically simplified to the architecture shown in Figure 5. In this example, parallel banks of VCSO-based PLLs, RF multiplexers, and hitless switching PLL circuitry can be eliminated and replaced with a single CMOS IC that is rate programmable via software control.

Conclusion

The conflict between the irresistible force of increasing system rate and protocol flexibility and the immovable object of fixed frequency timing sources is being resolved by the development of DSP-based high-performance clock sources that are frequency and phase agile. Along with the system-level benefits of software programmable data rates and protocols, board-level testing will be improved, increasing manufacturing yield and timing margin. The net effect of this new technology will be lower cost and more easily provisioned high-speed services to network customers.

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