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SN74LVT16952DGGR|TI|simage
SN74LVT16952DGGR|TI|limage
Bus Transceivers

SN74LVT16952DGGR

Bus XCVR Dual 16-CH 3-ST 56-Pin TSSOP T/R

Texas Instruments

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    8542.39.00.10
  • SVHC
    Yes
  • Automotive
    No
  • PPAP
    No
  • Logic Family
    LVT
  • Logic Function
    Registered Transceiver
  • Data Flow Direction
    Bi-Directional
  • Number of Elements per Chip
    2
  • Number of Channels per Chip
    16
  • Number of Selection Inputs per Element
    0
  • Number of Output Enables per Element
    2 Low
  • Number of Input Enables per Element
    2 Low
  • Number of Direction Control Inputs
    0
  • Bus Hold
    Yes
  • Triggering Type
    Positive-Edge
  • Polarity
    Non-Inverting
  • Absolute Propagation Delay Time (ns)
    8
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    3.4(Typ)@3.3V
  • Propagation Delay Test Condition (pF)
    50
  • Input Level
    LVTTL
  • Output Level
    LVTTL
  • Output Type
    3-State
  • Maximum Low Level Output Current (mA)
    64
  • Maximum High Level Output Current (mA)
    -32
  • Maximum Quiescent Current (uA)
    5000
  • Minimum Operating Supply Voltage (V)
    2.7
  • Maximum Operating Supply Voltage (V)
    3.6
  • Tolerant I/Os (V)
    5
  • Maximum Power Dissipation (mW)
    1000
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    85
  • Supplier Temperature Grade
    Commercial
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    1.05(Max) mm
  • Package Width
    6.2(Max) mm
  • Package Length
    14.1(Max) mm
  • PCB changed
    56
  • Standard Package Name
    SO
  • Supplier Package
    TSSOP
  • Pin Count
    56
  • Lead Shape
    Gull-wing

Documentation and Resources

Datasheets
Design resources