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MC100EP52MNR4G|ONSEMI|simage
MC100EP52MNR4G|ONSEMI|limage
Flip Flops

MC100EP52MNR4G

Flip Flop D-Master-Slave Type Pos-Edge/Neg-Edge 1-Element 8-Pin DFN EP T/R

onsemi
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    8542.39.00.90
  • Automotive
    No
  • PPAP
    No
  • Logic Family
    ECL
  • Logic Function
    D-Master-Slave Type
  • Number of Channels per Chip
    1
  • Number of Elements per Chip
    1
  • Number of Element Inputs
    1
  • Number of Element Outputs
    1
  • Bus Hold
    No
  • Polarity
    Inverting/Non-Inverting
  • Triggering Type
    Positive-Edge/Negative-Edge
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    0.38@3V to 5.5V
  • Absolute Propagation Delay Time (ns)
    0.41
  • Input Signal Type
    Differential
  • Maximum Low Level Output Current (mA)
    50
  • Maximum High Level Output Current (mA)
    -50
  • Minimum Operating Supply Voltage (V)
    -3|3
  • Typical Operating Supply Voltage (V)
    -3.3|-5|3.3|5
  • Maximum Operating Supply Voltage (V)
    -5.5|5.5
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    85
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    0.95(Max) mm
  • Package Width
    2 mm
  • Package Length
    2 mm
  • PCB changed
    8
  • Standard Package Name
    DFN
  • Supplier Package
    DFN EP
  • Pin Count
    8
  • Lead Shape
    No Lead

Documentation and Resources

Datasheets
Design resources