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M551225610SAC|LATTICE|simage
M551225610SAC|LATTICE|limage
Complex Programmable Logic Devices - CPLDs

M5-512/256-10SAC

CPLD MACH 5Family 20KGates 512Macro Cells 66.7MHz/100MHz 5V 352-Pin BGA Tray

Lattice Semiconductor
Datasheets 

Product Technical Specifications
  • EU RoHS
    Not Compliant
  • ECCN (US)
    3A001a.7.a.
  • Part Status
    Obsolete
  • HTS
    COMPONENTS
  • Automotive
    No
  • PPAP
    No
  • Family Name
    MACH 5
  • Program Memory Type
    ROMLess
  • Number of Global Clocks
    4
  • Number of Macro Cells
    512
  • Product Terms
    32
  • Device System Gates
    20000
  • Data Gate
    No
  • Maximum Number of User I/Os
    256
  • In-System Programmability
    Yes
  • Programmability
    Yes
  • Reprogrammability Support
    No
  • Maximum Internal Frequency (MHz)
    100|125
  • Maximum Internal Frequency (MHz)
    66.7|100
  • Maximum Clock to Output Delay (ns)
    12|7
  • Maximum Propagation Delay Time (ns)
    10
  • Speed Grade
    10
  • Individual Output Enable Control
    Yes
  • Minimum Operating Supply Voltage (V)
    4.75
  • Maximum Operating Supply Voltage (V)
    5.25
  • Typical Operating Supply Voltage (V)
    5
  • Tolerant Configuration Interface Voltage (V)
    5
  • Minimum Operating Temperature (°C)
    0
  • Maximum Operating Temperature (°C)
    70
  • Supplier Temperature Grade
    Commercial
  • Packaging
    Tray
  • Tradename
    MACH
  • Mounting
    Surface Mount
  • Package Height
    1.17
  • Package Width
    35
  • Package Length
    35
  • PCB changed
    352
  • Standard Package Name
    BGA
  • Supplier Package
    BGA
  • Pin Count
    352
  • Lead Shape
    Ball

Documentation and Resources

Datasheets
Design resources