Field Programmable Gate Arrays - FPGAs

LCMXO2-1200ZE-1SG32C

FPGA MachXO2Family 1280Cells 1.2V 32-Pin QFN EP Tray

Lattice Semiconductor

Product Technical Specifications

• EU RoHS

  Compliant

• ECCN (US)

  EAR99

• Part Status

  Active

• HTS

  8542.31.00.55

• Automotive

  No

• PPAP

  No

• Family Name

  MachXO2

• Process Technology

  65nm

• User I/Os

  21

• Number of I/O Banks

  4

• Operating Supply Voltage (V)

  1.2

• Shift Registers

  Utilize Memory

• Logic Elements

  1280

• Program Memory Type

  SRAM

• Embedded Memory (Kbit)

  64

• Total Number of Block RAM

  7

• Maximum Distributed RAM Bits

  10240

• Device Logic Units

  1280

• Device Number of DLLs/PLLs

  1

• Reprogrammability Support

  No

• In-System Programmability

  No

• Speed Grade

  1

• Maximum Differential I/O Pairs

  10

• Minimum Operating Supply Voltage (V)

  1.14

• Maximum Operating Supply Voltage (V)

  1.26

• I/O Voltage (V)

  1.2|1.5|1.8|2.5|3.3

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  85

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Mounting

  Surface Mount

• Package Height

  0.84

• Package Width

  5

• Package Length

  5

• PCB changed

  32

• Standard Package Name

  QFN

• Supplier Package

  QFN EP

• Pin Count

  32

• Lead Shape

  No Lead