Complex Programmable Logic Devices - CPLDs

LC5512MV-45F256C

CPLD ispXPLD 5000MVFamily 150KGates 512Macro Cells 275MHz 3.3V 256-Pin FBGA

Lattice Semiconductor

Product Technical Specifications

• EU RoHS

  Not Compliant

• ECCN (US)

  EAR99

• Part Status

  Obsolete

• HTS

  LC5512MV-45F256C

• SVHC

  Yes

• SVHC Exceeds Threshold

  Yes

• Automotive

  No

• PPAP

  No

• Family Name

  ispXPLD 5000MV

• Program Memory Type

  EEPROM

• Embedded Memory (Kbit)

  256

• Number of Logic Blocks/Elements

  16

• Number of Global Clocks

  4

• Number of I/O Banks

  4

• Number of Macro Cells

  512

• Product Terms

  160

• Device System Gates

  150000

• Data Gate

  No

• Maximum Number of User I/Os

  193

• In-System Programmability

  Yes

• Programmability

  Yes

• Reprogrammability Support

  Yes

• Maximum Internal Frequency (MHz)

  333

• Maximum Internal Frequency (MHz)

  275

• Maximum Clock to Output Delay (ns)

  3

• Maximum Propagation Delay Time (ns)

  4.5

• Speed Grade

  45

• Individual Output Enable Control

  No

• Minimum Operating Supply Voltage (V)

  3

• Maximum Operating Supply Voltage (V)

  3.6

• Typical Operating Supply Voltage (V)

  3.3

• Tolerant Configuration Interface Voltage (V)

  5

• Maximum Supply Current (mA)

  33(Typ)

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  90

• Supplier Temperature Grade

  Commercial

• Tradename

  ispXPLD

• Mounting

  Surface Mount

• Package Height

  1.2

• Package Width

  17

• Package Length

  17

• PCB changed

  256

• Standard Package Name

  BGA

• Supplier Package

  FBGA

• Pin Count

  256

• Lead Shape

  Ball