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LC4128V75TN128E|LATTICE|simage
LC4128V75TN128E|LATTICE|limage
Complex Programmable Logic Devices - CPLDs

LC4128V-75TN128E

CPLD ispMACH® 4000VFamily 128Macro Cells 168MHz 3.3V 128-Pin TQFP Tray

Lattice Semiconductor
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    8542.31.00.55
  • Automotive
    No
  • PPAP
    No
  • Family Name
    ispMACH® 4000V
  • Program Memory Type
    EEPROM
  • Number of Logic Blocks/Elements
    36
  • Number of Global Clocks
    4
  • Number of I/O Banks
    2
  • Number of Macro Cells
    128
  • Product Terms
    80
  • Data Gate
    No
  • Maximum Number of User I/Os
    92
  • In-System Programmability
    Yes
  • Programmability
    Yes
  • Reprogrammability Support
    Yes
  • Maximum Internal Frequency (MHz)
    168
  • Maximum Internal Frequency (MHz)
    168
  • Maximum Clock to Output Delay (ns)
    4.5
  • Maximum Propagation Delay Time (ns)
    7.5
  • Speed Grade
    75
  • Individual Output Enable Control
    Yes
  • Minimum Operating Supply Voltage (V)
    3
  • Maximum Operating Supply Voltage (V)
    3.6
  • Typical Operating Supply Voltage (V)
    3.3
  • Tolerant Configuration Interface Voltage (V)
    5
  • Maximum Supply Current (mA)
    12(Typ)
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    130
  • Supplier Temperature Grade
    Extended
  • Packaging
    Tray
  • Tradename
    ispMACH
  • Mounting
    Surface Mount
  • Package Height
    1.4 mm
  • Package Width
    14 mm
  • Package Length
    14 mm
  • PCB changed
    128
  • Standard Package Name
    QFP
  • Supplier Package
    TQFP
  • Pin Count
    128
  • Lead Shape
    Gull-wing

Documentation and Resources

Datasheets
Design resources