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LC4032ZC35MN56C|LATTICE|simage
LC4032ZC35MN56C|LATTICE|limage
Complex Programmable Logic Devices - CPLDs

LC4032ZC-35MN56C

CPLD ispMACH® 4000ZFamily 32Macro Cells 267MHz 1.8V 56-Pin CSBGA Tray

Lattice Semiconductor
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    8542.31.00.55
  • Automotive
    No
  • PPAP
    No
  • Family Name
    ispMACH® 4000Z
  • Program Memory Type
    EEPROM
  • Number of Logic Blocks/Elements
    36
  • Number of Global Clocks
    4
  • Number of I/O Banks
    2
  • Number of Macro Cells
    32
  • Product Terms
    80
  • Data Gate
    No
  • Maximum Number of User I/Os
    32
  • In-System Programmability
    Yes
  • Programmability
    Yes
  • Reprogrammability Support
    Yes
  • Maximum Internal Frequency (MHz)
    500
  • Maximum Internal Frequency (MHz)
    267
  • Maximum Clock to Output Delay (ns)
    3
  • Maximum Propagation Delay Time (ns)
    3.5
  • Speed Grade
    35
  • Individual Output Enable Control
    Yes
  • Minimum Operating Supply Voltage (V)
    1.7
  • Maximum Operating Supply Voltage (V)
    1.95
  • Typical Operating Supply Voltage (V)
    1.8
  • Tolerant Configuration Interface Voltage (V)
    5
  • Maximum Supply Current (mA)
    0.05(Typ)
  • Minimum Operating Temperature (°C)
    0
  • Maximum Operating Temperature (°C)
    90
  • Supplier Temperature Grade
    Commercial
  • Packaging
    Tray
  • Tradename
    ispMACH
  • Mounting
    Surface Mount
  • Package Height
    1.1(Max)
  • Package Width
    6
  • Package Length
    6
  • PCB changed
    56
  • Standard Package Name
    BGA
  • Supplier Package
    CSBGA
  • Pin Count
    56
  • Lead Shape
    Ball

Documentation and Resources

Datasheets
Design resources