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LA4032V75TN48E|LATTICE|limage
LA4032V75TN48E|LATTICE|simage
Complex Programmable Logic Devices - CPLDs

LA4032V-75TN48E

CPLD LA-ispMACH 4000VFamily 32Macro Cells 168MHz 3.3V 48-Pin TQFP Tray Automotive AEC-Q100

Lattice Semiconductor
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    COMPONENTS
  • Automotive
    Yes
  • PPAP
    Yes
  • Family Name
    LA-ispMACH 4000V
  • Program Memory Type
    EEPROM
  • Number of Logic Blocks/Elements
    2
  • Number of Global Clocks
    4
  • Number of I/O Banks
    2
  • Number of Macro Cells
    32
  • Product Terms
    80
  • Data Gate
    No
  • Maximum Number of User I/Os
    32
  • In-System Programmability
    Yes
  • Programmability
    Yes
  • Reprogrammability Support
    Yes
  • Maximum Internal Frequency (MHz)
    168
  • Maximum Clock to Output Delay (ns)
    4.5
  • Maximum Propagation Delay Time (ns)
    7.5
  • Speed Grade
    75
  • Individual Output Enable Control
    No
  • Minimum Operating Supply Voltage (V)
    3
  • Maximum Operating Supply Voltage (V)
    3.6
  • Typical Operating Supply Voltage (V)
    3.3
  • I/O Voltage (V)
    3.3|2.5|1.8
  • Tolerant Configuration Interface Voltage (V)
    5
  • Maximum Supply Current (mA)
    11.8(Typ)
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    125
  • Supplier Temperature Grade
    Automotive
  • Packaging
    Tray
  • Tradename
    ispMACH
  • Mounting
    Surface Mount
  • Package Height
    1
  • Package Width
    7
  • Package Length
    7
  • PCB changed
    48
  • Standard Package Name
    QFP
  • Supplier Package
    TQFP
  • Pin Count
    48
  • Lead Shape
    Gull-wing

Documentation and Resources

Datasheets
Design resources