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EPM7128STC10010N|ALTERA|simage
EPM7128STC10010N|ALTERA|limage
Complex Programmable Logic Devices - CPLDs

EPM7128STC100-10N

CPLD MAX® 7000SFamily 2.5KGates 128Macro Cells 100MHz 5V 100-Pin TQFP Tray

Altera
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Obsolete
  • HTS
    COMPONENTS
  • Automotive
    No
  • PPAP
    No
  • Family Name
    MAX® 7000S
  • Program Memory Type
    EEPROM
  • Number of Logic Blocks/Elements
    8
  • Number of Global Clocks
    2
  • Number of Macro Cells
    128
  • Product Terms
    32
  • Device System Gates
    2500
  • Data Gate
    No
  • Maximum Number of User I/Os
    84
  • In-System Programmability
    Yes
  • Programmability
    Yes
  • Reprogrammability Support
    Yes
  • Maximum Internal Frequency (MHz)
    125
  • Maximum Internal Frequency (MHz)
    100
  • Maximum Clock to Output Delay (ns)
    5
  • Maximum Propagation Delay Time (ns)
    10
  • Speed Grade
    10
  • Individual Output Enable Control
    Yes
  • Minimum Operating Supply Voltage (V)
    4.75
  • Maximum Operating Supply Voltage (V)
    5.25
  • Typical Operating Supply Voltage (V)
    5
  • I/O Voltage (V)
    3.3|5
  • Minimum Operating Temperature (°C)
    0
  • Maximum Operating Temperature (°C)
    70
  • Supplier Temperature Grade
    Commercial
  • Packaging
    Tray
  • Tradename
    MAX
  • Mounting
    Surface Mount
  • Package Height
    1
  • Package Width
    14
  • Package Length
    14
  • PCB changed
    100
  • Standard Package Name
    QFP
  • Supplier Package
    TQFP
  • Pin Count
    100
  • Lead Shape
    Gull-wing

Documentation and Resources

Datasheets
Design resources