Field Programmable Gate Arrays - FPGAs

EP3SE50F484C2G

FPGA Stratix® III EFamily 47500Cells 600MHz 1.1V 484-Pin FC-FBGA Tray

Altera

Product Technical Specifications

• EU RoHS

  Compliant

• Part Status

  NRND

• HTS

  8542.31.00.60

• Automotive

  No

• PPAP

  No

• Family Name

  Stratix® III E

• Process Technology

  65nm

• User I/Os

  296

• Number of I/O Banks

  24

• Operating Supply Voltage (V)

  1.1

• Shift Registers

  Utilize Memory

• Logic Elements

  47500

• Number of Multipliers

  384 (18x18)

• Program Memory Type

  SRAM

• Embedded Memory (Kbit)

  5625

• Total Number of Block RAM

  12+400+950

• IP Core

  Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|Multi-Channel HD/DCI JPEG 2000 Encoder (BA110)

• Provider Name

  Altera/CAST, Inc/Mobiveil, Inc/Eureka Technology Inc/Barco Silex

• Device Logic Units

  47500

• Number of Global Clocks

  16

• Device Number of DLLs/PLLs

  4

• Programmability

  No

• Reprogrammability Support

  No

• Copy Protection

  Yes

• Opr. Frequency (MHz)

  600

• In-System Programmability

  No

• Speed Grade

  2

• Differential I/O Standards

  LVPECL|LVDS

• Single-Ended I/O Standards

  LVTTL|LVCMOS

• External Memory Interface

  DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|QDRII+SRAM

• Minimum Operating Supply Voltage (V)

  1.05

• Maximum Operating Supply Voltage (V)

  1.15

• I/O Voltage (V)

  1.2|1.5|1.8|2.5|3.3

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  85

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  Stratix

• Mounting

  Surface Mount

• Package Height

  2.55

• Package Width

  23

• Package Length

  23

• PCB changed

  484

• Standard Package Name

  BGA

• Supplier Package

  FC-FBGA

• Pin Count

  484

• Lead Shape

  Ball