Field Programmable Gate Arrays - FPGAs
EP2S60F672I4
FPGA Stratix® IIFamily 60440Cells 711.24MHz 1.2V 672-Pin FC-FBGA Tray
AlteraProduct Technical Specifications
EU RoHS
Not Compliant
ECCN (US)
3A991d.
Part Status
Obsolete
HTS
COMPONENTS
SVHC
Yes
SVHC Exceeds Threshold
Yes
Automotive
No
PPAP
No
Family Name
Stratix® II
Process Technology
90nm
User I/Os
492
Number of I/O Banks
8
Operating Supply Voltage (V)
1.2
Shift Registers
Utilize Memory
Logic Elements
60440
Number of Multipliers
144 (18x18)
Program Memory Type
SRAM
Embedded Memory (Kbit)
2484.6
Total Number of Block RAM
2+255+329
IP Core
Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Provider Name
Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA
Device Logic Units
60440
Number of Global Clocks
16
Device Number of DLLs/PLLs
12
Dedicated DSP
36
Programmability
No
Reprogrammability Support
No
Copy Protection
No
Opr. Frequency (MHz)
711.24
In-System Programmability
Yes
Speed Grade
4
GMACs
37.8
Mega Multiply Accumulates per second
37800
Differential I/O Standards
LVPECL|LVDS
Single-Ended I/O Standards
LVTTL|CMOS|SSTL|HSTL
Maximum I/O Performance
1Gbps
External Memory Interface
DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM
Minimum Operating Supply Voltage (V)
1.15
Maximum Operating Supply Voltage (V)
1.25
I/O Voltage (V)
1.5|1.8|2.5|3.3
Minimum Operating Temperature (°C)
-40
Maximum Operating Temperature (°C)
100
Supplier Temperature Grade
Industrial
Packaging
Tray
Tradename
Stratix
Mounting
Surface Mount
Package Height
3(Max)
Package Width
27
Package Length
27
PCB changed
672
Standard Package Name
BGA
Supplier Package
FC-FBGA
Pin Count
672
Lead Shape
Ball