Field Programmable Gate Arrays - FPGAs
EP2S15F484C3N
FPGA Stratix® IIFamily 15600Cells 816.99MHz 1.2V 484-Pin FC-FBGA Tray
AlteraProduct Technical Specifications
EU RoHS
Compliant with Exemption
ECCN (US)
3A991d.
Part Status
Obsolete
HTS
8542.31.00.60
SVHC
Yes
SVHC Exceeds Threshold
Yes
Automotive
No
PPAP
No
Family Name
Stratix® II
Process Technology
90nm
User I/Os
342
Number of I/O Banks
8
Operating Supply Voltage (V)
1.2
Shift Registers
Utilize Memory
Logic Elements
15600
Number of Multipliers
48 (18x18)
Program Memory Type
SRAM
Embedded Memory (Kbit)
409.5
Total Number of Block RAM Memories
0+78+104
IP Core
Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Provider Name
Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA
Device Logic Units
15600
Number of Global Clocks
16
Device Number of DLLs/PLLs
6
Dedicated DSP
12
Programmability
No
Reprogrammability Support
No
Copy Protection
No
Opr. Frequency (MHz)
816.99
In-System Programmability
Yes
Speed Grade
3
GMACs
12.6
Mega Multiply Accumulates per Second
12600
Differential I/O Standards
LVPECL|LVDS
Single-Ended I/O Standards
LVTTL|CMOS|SSTL|HSTL
Maximum I/O Performance
1Gbps
External Memory Interface
DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM
Minimum Operating Supply Voltage (V)
1.15
Maximum Operating Supply Voltage (V)
1.25
I/O Voltage (V)
1.5|1.8|2.5|3.3
Minimum Operating Temperature (°C)
0
Maximum Operating Temperature (°C)
85
Supplier Temperature Grade
Commercial
Packaging
Tray
Tradename
Stratix
Mounting
Surface Mount
Package Height
3(Max)
Package Width
23
Package Length
23
PCB changed
484
Standard Package Name
BGA
Supplier Package
FC-FBGA
Pin Count
484
Lead Shape
Ball
Order Quantity