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74AUP2G32GS115|NEXPERIA|simage
74AUP2G32GS115|NEXPERIA|limage
Logic Gates

74AUP2G32GS,115

OR Gate 2-Element 2-IN 8-Pin XSON T/R

Nexperia
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    COMPONENTS
  • Automotive
    Yes
  • PPAP
    Unknown
  • Logic Family
    AUP
  • Logic Function
    OR
  • Number of Elements per Chip
    2
  • Number of Element Inputs
    2-IN
  • Number of Output Enables per Element
    0
  • Number of Selection Inputs per Element
    0
  • Number of Element Outputs
    1
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    19.1@1.1V to 1.3V|11.3@1.4V to 1.6V|8.9@1.65V to 1.95V|7@2.3V to 2.7V|6.4@3V to 3.6V
  • Absolute Propagation Delay Time (ns)
    23.7
  • Maximum Low Level Output Current (mA)
    4
  • Maximum High Level Output Current (mA)
    -4
  • Minimum Operating Supply Voltage (V)
    0.8
  • Typical Operating Supply Voltage (V)
    1.8|2.5|3.3
  • Maximum Operating Supply Voltage (V)
    3.6
  • Maximum Quiescent Current (uA)
    0.5
  • Propagation Delay Test Condition (pF)
    30
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    125
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    0.31(Max)
  • Package Width
    1
  • Package Length
    1.35
  • PCB changed
    8
  • Standard Package Name
    SON
  • Supplier Package
    XSON
  • Pin Count
    8

Documentation and Resources

Datasheets
Design resources