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74AUP1G86GW125|NEXPERIA|limage
74AUP1G86GW125|NEXPERIA|simage
Logic Gates

74AUP1G86GW,125

XOR Gate 1-Element 2-IN 5-Pin TSSOP T/R

Nexperia
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    8542.39.00.90
  • SVHC
    Yes
  • Automotive
    Yes
  • PPAP
    Unknown
  • Logic Family
    AUP
  • Logic Function
    XOR
  • Number of Elements per Chip
    1
  • Number of Element Inputs
    2-IN
  • Number of Output Enables per Element
    0
  • Number of Selection Inputs per Element
    0
  • Number of Element Outputs
    1
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    21.5@1.1V to 1.3V|12.5@1.4V to 1.6V|9.8@1.65V to 1.95V|7.6@2.3V to 2.7V|7.1@3V to 3.6V
  • Absolute Propagation Delay Time (ns)
    26.6
  • Maximum Low Level Output Current (mA)
    4
  • Maximum High Level Output Current (mA)
    -4
  • Minimum Operating Supply Voltage (V)
    0.8
  • Typical Operating Supply Voltage (V)
    3.3|2.5|1.8
  • Maximum Operating Supply Voltage (V)
    3.6
  • Maximum Quiescent Current (uA)
    0.5
  • Propagation Delay Test Condition (pF)
    30
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    125
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    1(Max)
  • Package Width
    1.35(Max)
  • Package Length
    2.2(Max)
  • PCB changed
    5
  • Standard Package Name
    SO
  • Supplier Package
    TSSOP
  • Pin Count
    5
  • Lead Shape
    Gull-wing

Documentation and Resources

Datasheets
Design resources