Phase-Locked Loops - PLLs

A Phased Lock Loop (PLL) is a control system that generates an output signal by aligning the phase of an incoming signal to that of the output signal. The key building blocks of a PLL are a phase-frequency detector (PFD), a low pass filter (LPF), and a Voltage Controlled Oscillator (VCO). The phase detector will output a control or error signal, proportional to the amount of difference in phase between a reference clock signal and a divided down feedback clock signal from the output of the same PLL. The VCO generates an output clock that is a multiple of the reference clock relative to the control voltage from the PFD. The output of the VCO is then fed back to the phase detector through a frequency divider to ensure its frequency is exactly the same as the reference input clock, thus closing the feedback loop. The LPF in a PLL system filters unwanted high frequency noise and helps to smooth the control voltage. The closed-loop characteristic of the PLL will cause the output clock signal to be locked or phase aligned to the reference clock. PLL circuits are commonly used in communications systems, computers, and other electronic systems. They are used as frequency multipliers for the generation of higher order frequencies that most inexpensive stand-alone oscillators aren't capable of. Due to their low cost and relatively good performance, they are preferred in designs over expensive high end oscillators.