CN-0003
Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using the ADF4002 PLL
설명
CN-0003, Application circuit utilizes the ADF4002 frequency synthesizer to generate a very low jitter encode (sampling) clock to control sampling on the AD9215 analog-to-digital converter. Jitter on the encode clock produces degradation in the overall signal-tonoise ratio (SNR). The ADF4002 consists of a low noise digital phase frequency detector (PFD), precision charge pump, programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO)
관련 부품
| 부품 번호 | 필터 유형 | 관련 부품 | 다운로드 |
|---|---|---|---|
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 65Msps 10-bit Parallel 28-Pin TSSOP Tube | ||
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 80Msps 10-bit Parallel 32-Pin LFCSP EP Tray | ||
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 65Msps 10-bit Parallel 32-Pin LFCSP EP Tray | ||
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 80Msps 10-bit Parallel 28-Pin TSSOP Tube | ||
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 105Msps 10-bit Parallel 28-Pin TSSOP Tube | ||
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 105Msps 10-bit Parallel 28-Pin TSSOP T/R | ||
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 65Msps 10-bit Parallel 28-Pin TSSOP T/R | ||
Analog to Digital Converters - ADCs | 1-Channel Single ADC Pipelined 105Msps 10-bit Parallel 32-Pin LFCSP EP Tray |
