복잡 프로그래머블 로직 장치 - CPLD

M4A3-64/64-7VNC

CPLD ispMACH 4AFamily 2.5KGates 64Macro Cells 105MHz/125MHz 3.3V 100-Pin TQFP Tray

Lattice Semiconductor

제품 기술 사양

• EU RoHS

  Compliant

• ECCN (US)

  EAR99

• Part Status

  Obsolete

• HTS

  8542.39.00.01

• Automotive

  No

• PPAP

  No

• Family Name

  ispMACH 4A

• Program Memory Type

  EEPROM

• Embedded Memory (Kbit)

  0

• Number of Global Clocks

  4

• Number of Macro Cells

  64

• Product Terms

  20

• Device System Gates

  2500

• Data Gate

  No

• Maximum Number of User I/Os

  64

• Number of Flip Flops

  96

• In-System Programmability

  Yes

• Programmability

  Yes

• Reprogrammability Support

  Yes

• Maximum Internal Frequency (MHz)

  125|154

• Maximum Internal Frequency (MHz)

  105|125

• Maximum Clock to Output Delay (ns)

  8.5|5.5

• Maximum Propagation Delay Time (ns)

  7.5

• Speed Grade

  7

• Individual Output Enable Control

  Yes

• Minimum Operating Supply Voltage (V)

  3

• Maximum Operating Supply Voltage (V)

  3.6

• Typical Operating Supply Voltage (V)

  3.3

• Tolerant Configuration Interface Voltage (V)

  5

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  70

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  ispMACH

• Mounting

  Surface Mount

• Package Height

  1.4 mm

• Package Width

  14 mm

• Package Length

  14 mm

• PCB changed

  100

• Standard Package Name

  QFP

• Supplier Package

  TQFP

• Pin Count

  100

• Lead Shape

  Gull-wing