Field Programmable Gate Arrays - FPGAs

EP3SL70F484I4G

FPGA Stratix® III LFamily 67500Cells 450MHz 1.1V 484-Pin FC-FBGA Tray

Altera

제품 기술 사양

• RoHS (Unione Europea)

  Compliant

• Stato del componente

  NRND

• Codice HTS

  8542.31.00.60

• Automotive

  No

• PPAP

  No

• Family Name

  Stratix® III L

• Process Technology

  65nm

• User I/Os

  296

• Number of I/O Banks

  24

• Operating Supply Voltage (V)

  1.1

• Shift Registers

  Utilize Memory

• Logic Elements

  67500

• Number of Multipliers

  288 (18x18)

• Program Memory Type

  SRAM

• Embedded Memory (Kbit)

  2636

• Total Number of Block RAM Memories

  6+150+1350

• IP Core

  Sub-frame Latency JPEG 2000 Encoder (BA130)|RapidIO to AXI Bridge Controller (RAB)|EtherCAT|EtherNET/IP|DS1/E1 TDM over Packet IP core

• Provider Name

  Barco Silex/Mobiveil, Inc

• Device Logic Units

  67500

• Number of Global Clocks

  16

• Device Number of DLLs/PLLs

  4

• Programmability

  No

• Reprogrammability Support

  No

• Copy Protection

  Yes

• Opr. Frequency (MHz)

  450

• In-System Programmability

  No

• Speed Grade

  4

• Differential I/O Standards

  LVPECL|LVDS

• Single-Ended I/O Standards

  LVTTL|LVCMOS

• External Memory Interface

  DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|QDRII+SRAM

• Minimum Operating Supply Voltage (V)

  1.05

• Maximum Operating Supply Voltage (V)

  1.15

• I/O Voltage (V)

  1.2|1.5|1.8|2.5|3.3

• Minimum Operating Temperature (°C)

  -40

• Maximum Operating Temperature (°C)

  100

• Supplier Temperature Grade

  Industrial

• Packaging

  Tray

• Tradename

  Stratix

• Mounting

  Surface Mount

• Package Height

  2.55

• Package Width

  23

• Package Length

  23

• PCB changed

  484

• Standard Package Name

  BGA

• Supplier Package

  FC-FBGA

• Pin Count

  484

• Lead Shape

  Ball