Field Programmable Gate Arrays - FPGAs
EP2S30F672C3N
FPGA Stratix® IIFamily 33880Cells 816.99MHz 1.2V 672-Pin FC-FBGA Tray
AlteraSpecifiche Tecniche del Prodotto
RoHS (Unione Europea)
Compliant with Exemption
ECCN (Stati Uniti)
3A001a.7.a.
Stato del componente
Obsolete
Codice HTS
COMPONENTS
Automotive
No
PPAP
No
Family Name
Stratix® II
Process Technology
90nm
User I/Os
500
Number of I/O Banks
8
Operating Supply Voltage (V)
1.2
Shift Registers
Utilize Memory
Logic Elements
33880
Number of Multipliers
64 (18x18)
Program Memory Type
SRAM
Embedded Memory (Kbit)
1337.6
Total Number of Block RAM
1+144+202
IP Core
Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Provider Name
Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA
Device Logic Units
33880
Number of Global Clocks
16
Device Number of DLLs/PLLs
6
Dedicated DSP
16
Programmability
No
Reprogrammability Support
No
Copy Protection
No
Opr. Frequency (MHz)
816.99
In-System Programmability
Yes
Speed Grade
3
GMACs
16.8
Mega Multiply Accumulates per second
16800
Differential I/O Standards
LVPECL|LVDS
Single-Ended I/O Standards
LVTTL|CMOS|SSTL|HSTL
Maximum I/O Performance
1Gbps
External Memory Interface
DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM
Minimum Operating Supply Voltage (V)
1.15
Maximum Operating Supply Voltage (V)
1.25
I/O Voltage (V)
1.5|1.8|2.5|3.3
Minimum Operating Temperature (°C)
0
Maximum Operating Temperature (°C)
85
Supplier Temperature Grade
Commercial
Packaging
Tray
Tradename
Stratix
Mounting
Surface Mount
Package Height
3(Max)
Package Width
27
Package Length
27
PCB changed
672
Standard Package Name
BGA
Supplier Package
FC-FBGA
Pin Count
672
Lead Shape
Ball