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SN74LV125AN|TI|simage
SN74LV125AN|TI|limage
Buffers and Line Drivers

SN74LV125AN

Buffer/Line Driver 4-CH Non-Inverting 3-ST 14-Pin PDIP Tube

Texas Instruments

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    8542.39.00.90
  • Automotive
    No
  • PPAP
    No
  • Logic Family
    LV
  • Logic Function
    Buffer/Line Driver
  • Number of Elements per Chip
    4
  • Number of Channels per Chip
    4
  • Number of Inputs per Chip
    4
  • Number of Input Enables per Chip
    0
  • Number of Outputs per Chip
    4
  • Number of Output Enables per Chip
    4 Low
  • Bus Hold
    No
  • Polarity
    Non-Inverting
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    7.5@5V|11.5@3.3V|16.5@2.5V
  • Absolute Propagation Delay Time (ns)
    20.5
  • Input Signal Type
    Single-Ended
  • Output Type
    3-State
  • Maximum Low Level Output Current (mA)
    16
  • Maximum High Level Output Current (mA)
    -16
  • Minimum Operating Supply Voltage (V)
    2
  • Typical Operating Supply Voltage (V)
    5|3.3|2.5
  • Maximum Operating Supply Voltage (V)
    5.5
  • Tolerant I/Os (V)
    5.5 Inputs
  • Maximum Quiescent Current (uA)
    20
  • Propagation Delay Test Condition (pF)
    50
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    125
  • Packaging
    Tube
  • Mounting
    Through Hole
  • Package Height
    5.08(Max) - 0.51(Min)
  • Package Width
    6.35
  • Package Length
    19.31
  • PCB changed
    14
  • Standard Package Name
    DIP
  • Supplier Package
    PDIP
  • Pin Count
    14
  • Lead Shape
    Through Hole

Documentation and Resources

Datasheets
Design resources