CPLDs

M4A5-256/128-65YNC

CPLD ispMACH 4AFamily 10KGates 256Macro Cells 125MHz/154MHz 5V 208-Pin PQFP Tray

Lattice Semiconductor

Product Technical Specifications

• RoHS (Unión Europea)

  Compliant

• ECCN (Estados Unidos)

  EAR99

• Estatus de pieza

  Obsolete

• Código HTS

  EA

• Automotive

  No

• PPAP

  No

• Family Name

  ispMACH 4A

• Program Memory Type

  EEPROM

• Number of Global Clocks

  4

• Number of Macro Cells

  256

• Product Terms

  20

• Device System Gates

  10000

• Data Gate

  No

• Maximum Number of User I/Os

  128

• Number of Flip Flops

  384

• In-System Programmability

  Yes

• Programmability

  Yes

• Reprogrammability Support

  Yes

• Maximum Internal Frequency (MHz)

  143|200

• Maximum Internal Frequency (MHz)

  125|154

• Maximum Clock to Output Delay (ns)

  7|5

• Maximum Propagation Delay Time (ns)

  6.5

• Speed Grade

  65

• Individual Output Enable Control

  Yes

• Minimum Operating Supply Voltage (V)

  4.75

• Maximum Operating Supply Voltage (V)

  5.25

• Typical Operating Supply Voltage (V)

  5

• Tolerant Configuration Interface Voltage (V)

  5

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  70

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  ispMACH

• Mounting

  Surface Mount

• Package Height

  3.4 mm

• Package Width

  28 mm

• Package Length

  28 mm

• PCB changed

  208

• Standard Package Name

  QFP

• Supplier Package

  PQFP

• Pin Count

  208

• Lead Shape

  Gull-wing