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IS62WV51216BLL55TLITR|ISSI|simage
IS62WV51216BLL55TLITR|ISSI|limage
SRAM Chip

IS62WV51216BLL-55TLI-TR

SRAM Chip Async Single 3.3V 8M-bit 512K x 16 55ns 44-Pin TSOP-II T/R

Integrated Silicon Solution Inc
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    3A991b.2.a.
  • Part Status
    Active
  • HTS
    8542.32.00.41
  • Automotive
    No
  • PPAP
    No
  • Chip Density (bit)
    8M
  • Number of Words
    512K
  • Number of Bits/Word (bit)
    16
  • Data Rate Architecture
    SDR
  • Address Bus Width (bit)
    19
  • Number of Ports
    1
  • Timing Type
    Asynchronous
  • Max. Access Time (ns)
    55
  • Minimum Operating Supply Voltage (V)
    2.5
  • Typical Operating Supply Voltage (V)
    3.3
  • Maximum Operating Supply Voltage (V)
    3.6
  • Operating Current (mA)
    35
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    85
  • Supplier Temperature Grade
    Industrial
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    1.05(Max)
  • Package Width
    10.29(Max)
  • Package Length
    18.52(Max)
  • PCB changed
    44
  • Standard Package Name
    SO
  • Supplier Package
    TSOP-II
  • Pin Count
    44
  • Lead Shape
    Gull-wing

Documentation and Resources

Datasheets
Design resources