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IS62WV12816BLL55B2LITR|ISSI|simage
IS62WV12816BLL55B2LITR|ISSI|limage
SRAM Chip

IS62WV12816BLL-55B2LI-TR

SRAM Chip Async Single 3.3V 2M-bit 128K x 16 55ns 48-Pin TFBGA T/R

Integrated Silicon Solution Inc
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    3A991b.2.a.
  • Part Status
    Active
  • HTS
    8542.32.00.41
  • Automotive
    No
  • PPAP
    No
  • Chip Density (bit)
    2M
  • Number of Words
    128K
  • Number of Bits/Word (bit)
    16
  • Data Rate Architecture
    SDR
  • Address Bus Width (bit)
    17
  • Number of Ports
    1
  • Timing Type
    Asynchronous
  • Max. Access Time (ns)
    55
  • Minimum Operating Supply Voltage (V)
    2.5
  • Typical Operating Supply Voltage (V)
    3.3
  • Maximum Operating Supply Voltage (V)
    3.6
  • Operating Current (mA)
    3
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    85
  • Supplier Temperature Grade
    Industrial
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    0.9(Max)
  • Package Width
    6
  • Package Length
    8
  • PCB changed
    48
  • Standard Package Name
    BGA
  • Supplier Package
    TFBGA
  • Pin Count
    48
  • Lead Shape
    Ball

Documentation and Resources

Datasheets
Design resources