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CY7C1423KV18300BZC|INFINEON|simage
CY7C1423KV18300BZC|INFINEON|limage
SRAM Chip

CY7C1423KV18-300BZC

SRAM Chip Sync Dual 1.8V 36M-bit 2M x 18 0.45ns 165-Pin FBGA Tray

Infineon Technologies AG
Datasheets 

Product Technical Specifications
  • EU RoHS
    Not Compliant
  • ECCN (US)
    3A991b.2.a.
  • Part Status
    Obsolete
  • HTS
    CY7C1423KV18-300BZC
  • Automotive
    No
  • PPAP
    No
  • Chip Density (bit)
    36M
  • Number of Words
    2M
  • Number of Bits/Word (bit)
    18
  • Architecture
    Pipelined
  • Data Rate Architecture
    DDR
  • Address Bus Width (bit)
    20
  • Number of Ports
    2
  • Timing Type
    Synchronous
  • Max. Access Time (ns)
    0.45
  • Maximum Clock Rate (MHz)
    300
  • Minimum Operating Supply Voltage (V)
    1.7
  • Typical Operating Supply Voltage (V)
    1.8
  • Maximum Operating Supply Voltage (V)
    1.9
  • Operating Current (mA)
    460
  • Minimum Operating Temperature (°C)
    0
  • Maximum Operating Temperature (°C)
    70
  • Supplier Temperature Grade
    Commercial
  • Packaging
    Tray
  • Mounting
    Surface Mount
  • Package Height
    0.89
  • Package Width
    13
  • Package Length
    15
  • PCB changed
    165
  • Standard Package Name
    BGA
  • Supplier Package
    FBGA
  • Pin Count
    165
  • Lead Shape
    Ball

Documentation and Resources

Datasheets
Design resources