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CD74HC107MT|TI|simage
CD74HC107MT|TI|limage
Flip Flops

CD74HC107MT

Flip Flop JK-Type Neg-Edge Push-Pull 2-Element 14-Pin SOIC T/R

Texas Instruments

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Obsolete
  • HTS
    CD74HC107MT
  • SVHC
    Yes
  • Automotive
    No
  • PPAP
    No
  • Logic Family
    HC
  • Logic Function
    JK-Type
  • Number of Channels per Chip
    2
  • Number of Elements per Chip
    2
  • Number of Element Inputs
    2
  • Number of Element Outputs
    1
  • Bus Hold
    No
  • Set/Reset
    Reset
  • Polarity
    Inverting/Non-Inverting
  • Triggering Type
    Negative-Edge
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    170@2V|34@4.5V|29@6V
  • Absolute Propagation Delay Time (ns)
    255
  • Input Signal Type
    Single-Ended
  • Output Type
    Push-Pull
  • Maximum Low Level Output Current (mA)
    5.2
  • Maximum High Level Output Current (mA)
    -5.2
  • Minimum Operating Supply Voltage (V)
    2
  • Typical Operating Supply Voltage (V)
    2.5|3.3|5
  • Maximum Operating Supply Voltage (V)
    6
  • Maximum Quiescent Current (mA)
    0.004
  • Propagation Delay Test Condition (pF)
    50
  • Minimum Operating Temperature (°C)
    -55
  • Maximum Operating Temperature (°C)
    125
  • Supplier Temperature Grade
    Military
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    1.5(Max)
  • Package Width
    3.9
  • Package Length
    8.65
  • PCB changed
    14
  • Standard Package Name
    SO
  • Supplier Package
    SOIC
  • Pin Count
    14
  • Lead Shape
    Gull-wing

Documentation and Resources

Datasheets
Design resources