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74LV02APWJ|NEXPERIA|limage
74LV02APWJ|NEXPERIA|simage
Logic Gates

74LV02APWJ

NOR Gate 4-Element 2-IN 14-Pin TSSOP T/R

Nexperia
Datasheets 

Product Technical Specifications
  • EU RoHS
    Compliant
  • ECCN (US)
    EAR99
  • Part Status
    Active
  • HTS
    8542.39.00.90
  • Automotive
    No
  • PPAP
    No
  • Logic Family
    LV
  • Logic Function
    NOR
  • Number of Elements per Chip
    4
  • Number of Element Inputs
    2-IN
  • Number of Output Enables per Element
    0
  • Number of Selection Inputs per Element
    0
  • Number of Element Outputs
    1
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    16.1@2.5V|11.4@3.3V|7.5@5V
  • Absolute Propagation Delay Time (ns)
    19
  • Maximum Low Level Output Current (mA)
    12
  • Maximum High Level Output Current (mA)
    -12
  • Minimum Operating Supply Voltage (V)
    2
  • Typical Operating Supply Voltage (V)
    5
  • Maximum Operating Supply Voltage (V)
    5.5
  • Maximum Quiescent Current (uA)
    20
  • Propagation Delay Test Condition (pF)
    50
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    125
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    1.05(Max) mm
  • Package Width
    4.5(Max) mm
  • Package Length
    5.1(Max) mm
  • PCB changed
    14
  • Standard Package Name
    SO
  • Supplier Package
    TSSOP
  • Pin Count
    14

Documentation and Resources

Datasheets
Design resources