A digital crosspoint is a device that can switch any of its inputs to any of its outputs. Inputs and outputs are digital, active, and are not bidirectional. They come in a variety of sizes and can even be up to 20x20 in size on a single chip. '20x20' means 20 inputs to 20 outputs, any of the 20 inputs could connect to any of the 20 outputs. A digital crosspoint is usually oriented towards high-speed signal switching , with some crosspoints being able to switch 12Gbits/s or higher data rates.

An important characteristic of crosspoints is that they can interface to high-speed signaling standards. They typically support PECL (pseudo emitter coupled logic) or CML (current mode logic) differential inputs and outputs. These inputs and outputs are referred to as receivers and transmitters respectively. To support such high data rates, equalization (amplitude and phase compensation filters) are implemented on the receivers of the Crosspoint to compensate for circuit board (PCB) losses. Transmitters can also have a special feed forward equalization to pre-compensate for board losses. Equalization and on both inputs and outputs allows longer PCB traces to be supported.

Crosspoints have per-lane loss of signal detection. They have an SPI or I2C serial interface complying with standard CMOS or TTL logic that can be used to configure the crosspoint's interconnection map. They also typically have the ability to automatically load a map from a serial interfacing EEPROM upon power up.

Crosspoints are typically utilized in applications like fiber optic network switching, SONET C-192/STM-64x, 10Gbit Ethernet and SDI video. Digital communications standards require low noise, referred to as jitter. Crosspoints are designed to minimize how much phase jitter they add to a signal. For a Crosspoint to be able to be used, the combined phase jitter that must be less than the communications standards maximum jitter specifications. In some really large crosspoint designs, where a special purpose IC is not available, FPGAs with high-speed transceivers are used to implement the crosspoint. Many FPGA designs also incorporate a process called reclocking that regenerates the digital stream around a new, clean clock before transmitting which allows many crosspoints to be cascaded.