Field Programmable Gate Arrays - FPGAs

EP20K100ETC144-1X

FPGA APEX 20KFamily 100KGates 4160Cells 250MHz 1.8V 144-Pin TQFP Tray

Altera

产品技术规范

• 欧盟RoHS指令

  Not Compliant

• 美国出口管制分类ECCN编码

  EAR99

• 环保无铅

  Obsolete

• 美国海关商品代码

  COMPONENTS

• Automotive

  No

• PPAP

  No

• Family Name

  APEX 20K

• Process Technology

  0.18um

• User I/Os

  92

• Number of I/O Banks

  8

• Operating Supply Voltage (V)

  1.8

• Logic Elements

  4160

• Device System Gates

  263000

• Program Memory Type

  SRAM

• Embedded Memory (Kbit)

  52

• Total Number of Block RAM Memories

  26

• Device Logic Gates

  100000

• Device Logic Units

  4160

• Number of Global Clocks

  8

• Device Number of DLLs/PLLs

  2

• Programmability

  No

• Reprogrammability Support

  No

• Copy Protection

  No

• Opr. Frequency (MHz)

  250

• In-System Programmability

  No

• Speed Grade

  1

• Differential I/O Standards

  LVPECL, LVDS, PCI-X, AGP, CTT

• Single-Ended I/O Standards

  LVTTL, LVCMOS

• Maximum I/O Performance

  840Mbps

• External Memory Interface

  DDR SDRAM, ZBT SRAM

• Minimum Operating Supply Voltage (V)

  1.71

• Maximum Operating Supply Voltage (V)

  1.89

• I/O Voltage (V)

  1.8, 2.5, 3.3

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  85

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  APEX

• Mounting

  Surface Mount

• Package Height

  1.4

• Package Width

  20

• Package Length

  20

• PCB changed

  144

• Standard Package Name

  QFP

• Supplier Package

  TQFP

• Pin Count

  144

• Lead Shape

  Gull-wing

• Family/Series

  EP20K100E

• ROHS Version

  2011/65/EU, 2015/863

• MSL

  3