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Field Programmable Gate Arrays - FPGAs

EP1K50TC1441N | ACEX 1K PLD

FPGA ACEX 1KFamily 50KGates 2880Cells 250MHz 2.5V 144-Pin TQFP Tray

Altera

产品技术规范

• 欧盟RoHS指令

  Compliant

• 美国出口管制分类ECCN编码

  EAR99

• 环保无铅

  Obsolete

• 美国海关商品代码

  COMPONENTS

• Automotive

  No

• PPAP

  No

• Family Name

  ACEX 1K

• Process Technology

  0.22um

• User I/Os

  102

• Number of Inter Dielectric Layers

  5

• Operating Supply Voltage (V)

  2.5

• Logic Elements

  2880

• Device System Gates

  199000

• Program Memory Type

  SRAM

• Embedded Memory (Kbit)

  40

• Total Number of Block RAM

  10

• Device Logic Gates

  50000

• Device Logic Units

  2880

• Number of Global Clocks

  6

• Device Number of DLLs/PLLs

  1

• Programmability

  No

• Reprogrammability Support

  No

• Copy Protection

  Yes

• Opr. Frequency (MHz)

  250

• In-System Programmability

  No

• Speed Grade

  1

• Single-Ended I/O Standards

  LVTTL|LVCMOS

• Minimum Operating Supply Voltage (V)

  2.375

• Maximum Operating Supply Voltage (V)

  2.625

• I/O Voltage (V)

  2.5|3.3

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  70

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  ACEX

• Mounting

  Surface Mount

• Package Height

  1.4

• Package Width

  20

• Package Length

  20

• PCB changed

  144

• Standard Package Name

  QFP

• Supplier Package

  TQFP

• Pin Count

  144

• Lead Shape

  Gull-wing