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74LVCH16245ADL118|NEXPERIA|simage
74LVCH16245ADL118|NEXPERIA|limage
总线收发器

74LVCH16245ADL,118

Bus XCVR Dual 16-CH 3-ST 48-Pin SSOP T/R

Nexperia
数据表 

产品技术规范
  • RoHS (Unione Europea)
    Compliant
  • ECCN (Stati Uniti)
    EAR99
  • Stato del componente
    Obsolete
  • Codice HTS
    COMPONENTS
  • Automotive
    No
  • PPAP
    No
  • Logic Family
    LVC
  • Logic Function
    Bus Transceiver
  • Data Flow Direction
    Bi-Directional
  • Number of Elements per Chip
    2
  • Number of Channels per Chip
    16
  • Number of Selection Inputs per Element
    0
  • Number of Output Enables per Element
    1 Low
  • Number of Input Enables per Element
    0
  • Number of Direction Control Inputs
    1 Low/High
  • Bus Hold
    Yes
  • Polarity
    Non-Inverting
  • Absolute Propagation Delay Time (ns)
    16.9
  • Maximum Propagation Delay Time @ Maximum CL (ns)
    2.7(Typ)@2.7V|2.4(Typ)@3.3V
  • Propagation Delay Test Condition (pF)
    50
  • Input Level
    LVTTL
  • Output Level
    LVTTL
  • Output Type
    3-State
  • Maximum Low Level Output Current (mA)
    24
  • Maximum High Level Output Current (mA)
    -24
  • Typical Quiescent Current (uA)
    0.1
  • Maximum Quiescent Current (uA)
    80
  • Minimum Operating Supply Voltage (V)
    1.2
  • Maximum Operating Supply Voltage (V)
    3.6
  • Tolerant I/Os (V)
    5
  • Maximum Power Dissipation (mW)
    500
  • Minimum Operating Temperature (°C)
    -40
  • Maximum Operating Temperature (°C)
    125
  • Packaging
    Tape and Reel
  • Mounting
    Surface Mount
  • Package Height
    2.35(Max)
  • Package Width
    7.6(Max)
  • Package Length
    16(Max)
  • PCB changed
    48
  • Standard Package Name
    SO
  • Supplier Package
    SSOP
  • Pin Count
    48

文档和资源

数据表
设计资源