複雑なプログラマブルロジックデバイス - CPLDs

M4A3-512/192-12FANC

CPLD ispMACH 4AFamily 20KGates 512Macro Cells 66.7MHz/95MHz 3.3V 256-Pin FBGA Tray

Lattice Semiconductor

製品技術仕様

• EU RoHS

  Compliant

• ECCN (US)

  EAR99

• Part Status

  Obsolete

• HTS

  8542.31.00.55

• Automotive

  No

• PPAP

  No

• Family Name

  ispMACH 4A

• Program Memory Type

  EEPROM

• Number of Global Clocks

  4

• Number of Macro Cells

  512

• Product Terms

  20

• Device System Gates

  20000

• Data Gate

  No

• Maximum Number of User I/Os

  192

• Number of Flip Flops

  768

• In-System Programmability

  Yes

• Programmability

  Yes

• Reprogrammability Support

  Yes

• Maximum Internal Frequency (MHz)

  62.5|100

• Maximum Internal Frequency (MHz)

  66.7|95

• Maximum Clock to Output Delay (ns)

  13|6.5

• Maximum Propagation Delay Time (ns)

  12

• Speed Grade

  12

• Individual Output Enable Control

  Yes

• Minimum Operating Supply Voltage (V)

  3

• Maximum Operating Supply Voltage (V)

  3.6

• Typical Operating Supply Voltage (V)

  3.3

• Tolerant Configuration Interface Voltage (V)

  5

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  70

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  ispMACH

• Mounting

  Surface Mount

• Package Height

  1.2

• Package Width

  17

• Package Length

  17

• PCB changed

  256

• Standard Package Name

  BGA

• Supplier Package

  FBGA

• Pin Count

  256

• Lead Shape

  Ball