Complex Programmable Logic Devices - CPLDs

EPM570GT144C5N

CPLD MAX® IIFamily 440Macro Cells 201.1MHz 1.8V 144-Pin TQFP Tray

Altera

产品技术规范

• 欧盟RoHS指令

  Compliant

• 美国出口管制分类ECCN编码

  EAR99

• 环保无铅

  NRND

• 美国海关商品代码

  8542.31.00.55

• Automotive

  No

• PPAP

  No

• Family Name

  MAX® II

• Logic Elements

  570

• Program Memory Type

  Flash

• Memory Size (Kbit)

  8

• Number of Logic Blocks/Elements

  57

• Number of Global Clocks

  4

• Number of I/O Banks

  2

• Number of Macro Cells

  440

• Process Technology

  0.18um

• Data Gate

  No

• Maximum Number of User I/Os

  116

• In-System Programmability

  Yes

• Number of Inter Dielectric Layers

  6

• Programmability

  Yes

• Reprogrammability Support

  No

• Maximum Internal Frequency (MHz)

  1879.7

• Maximum Internal Frequency (MHz)

  201.1

• Maximum Clock to Output Delay (ns)

  7.1

• Maximum Propagation Delay Time (ns)

  8.7

• Speed Grade

  5

• Individual Output Enable Control

  Yes

• Minimum Operating Supply Voltage (V)

  1.71

• Maximum Operating Supply Voltage (V)

  1.89

• Typical Operating Supply Voltage (V)

  1.8

• I/O Voltage (V)

  3.3|2.5|1.5|1.8

• Tolerant Configuration Interface Voltage (V)

  1.8|2.5|3.3|5

• Minimum Operating Temperature (°C)

  0

• Maximum Operating Temperature (°C)

  85

• Supplier Temperature Grade

  Commercial

• Packaging

  Tray

• Tradename

  MAX

• Mounting

  Surface Mount

• Package Height

  1.4

• Package Width

  20

• Package Length

  20

• PCB changed

  144

• Standard Package Name

  QFP

• Supplier Package

  TQFP

• Pin Count

  144

• Lead Shape

  Gull-wing